Datasheet

LM5070
SNVS308G –OCTOBER 2004–REVISED APRIL 2013 www.ti.com
Detailed Operating Description
The LM5070 power interface port and pulse width modulation (PWM) controller provides a complete integrated
solution for Powered Devices (PD) that connect into Power over Ethernet (PoE) systems. Major features of the
PD interface portion of the IC include detection, classification, programmable inrush current limit, thermal limit,
programmable undervoltage lockout, and current limit monitoring. The device also includes a high-voltage start-
up bias regulator that operates over a wide input range up to 75V. The switch mode power supply (SMPS)
control portion of the IC includes power good sensing, V
CC
regulator under-voltage lockout, cycle-by-cycle current
limit, error amplifier, slope compensation, softstart, and oscillator sync capability. This high speed BiCMOS IC
has total propagation delays less than 100ns and a 1MHz capable oscillator programmed by a single external
resistor. The LM5070 PWM controller provides current-mode control for dc-dc converter topologies requiring a
single drive output, such as Flyback and Forward topologies. The LM5070 PWM enables all of the advantages of
current-mode control including line feed-forward, cycle-by-cycle current limit and simplified loop compensation.
The oscillator ramp is internally buffered and added to the PWM comparator input ramp to provide slope
compensation necessary for current mode control at duty cycles greater than 50% (-80 suffix only).
Modes of Operation
The LM5070 PD interface is designed to provide a fully compliant IEEE 802.3af system. As such, the modes of
operation take into account the barrel rectifiers often utilized to correctly polarize the dc input from the Ethernet
cable. Table 1 shows the LM5070 operating modes and associated input voltage range.
Table 1. Operating Modes With Respect to Input Voltage
Input Voltage V
IN
wrt V
EE
Mode of Operation
1.8V to 10.0V Detection (Signature)
12.5V to 20.5V Classification
23.0V to UVLO Rising Vth Awaiting Full Power
75V to UVLO Falling Vth Normal Powered Operation
An external signature resistor is connected to V
EE
when V
IN
exceeds 1.8V, initiating detection mode. During
detection mode, quiescent current drawn by the LM5070 is less than 10uA. Between 10.0V and 12.5V, the
device enters classification mode and the signature resistor is disabled. The nominal range for classification
mode is 11.5V to 21.5V. The classification current is turned off once the classification range voltage is exceeded,
to reduce power dissipation. Between 21.5V and UVLO release, the device is in a standby state, awaiting the
input voltage to reach the operational range to complete the power up sequence. Once the V
IN
voltage increases
above the upper UVLO threshold voltage, the internal power MOSFET is enabled to deliver a constant current to
charge the input capacitor of the dc-dc converter. When the MOSFET Vds voltage falls below 1.5V, the internal
Power Good signal enables the SMPS controller. The LM5070 is specified to operate with an input voltage as
high as 75V. The SMPS controller and internal MOSFET are disabled when V
IN
falls to the lower UVLO
threshold.
Detection Signature
To detect a potential powered device candidate, the PSE will apply a voltage from 2.8V to 10V across the input
terminals of the PD. The voltage can be of either polarity so a diode barrel network is required on both lines to
ensure this capability. The PSE will take two measurements, separated by at least 1V and 2ms of time. The
voltage ramp between measurement points will not exceed 0.1V/us. The delta voltage / delta current calculation
is then performed; if the detected impedance is above 23.75kΩ and below 26.25kΩ, the PSE will consider a PD
to be present. If the impedance is less than 15kΩ or greater than 33kΩ a PD will be considered not present and
will not receive power. Impedances between these values may or may not indicate the presence of a valid PD.
The LM5070 will enable the signature resistor at a controller input voltage of 1.5V to take into account the diode
voltage drops. The PSE will tolerate no more than 1.9V of offset voltage (caused by the external diodes) or more
than 10uA of offset current (bias current). The input capacitance must be greater than 0.05uF and less than
0.12uF. To increase efficiency, the signature resistor is disabled by the LM5070 controller once the input voltage
is above the detection range (> 11V).
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