Datasheet

a)
Delay Rising Edge Only
b)
Long delay at rising edge,
short delay at falling edge
c)
Short Delay at Rising Edge and
Long Delay at Falling Edge or
Equal Delays
GND
PGD
R
PG1
LM5069
V
PGD
Power
Good
C
PG
GND
PGD
R
PG1
LM5069
V
PGD
Power
Good
C
PG
GND
PGD
R
PG1
LM5069
V
PGD
Power
Good
C
PG
R
PG2
R
PG2
LM5069
www.ti.com SNVS452D –SEPTEMBER 2006–REVISED MAY 2013
Figure 37. Adding Delay to the Power Good Output Pin
Design-in Procedure
The recommended design-in procedure is as follows:
• Determine the current limit threshold (I
LIM
). This threshold must be higher than the normal maximum load
current, allowing for tolerances in the current sense resistor value and the LM5069 Current Limit threshold
voltage. Use Equation 1 to determine the value for R
S
.
• Determine the maximum allowable power dissipation for the series pass FET (Q1), using the device’s SOA
information. Use Equation 2 to determine the value for R
PWR
.
• Determine the value for the timing capacitor at the TIMER pin (C
T
) using Equation 3. The fault timeout period
(t
FAULT
) must be longer than the circuit’s turn-on-time. The turn-on time can be estimated using the equations
in the Turn-on Time section of this data sheet, but should be verified experimentally. Review the resulting
insertion time, and restart timing if the LM5069-2 is used.
• Choose option A, B, C, or D from the UVLO, OVLO section of the Application Information for setting the
UVLO and OVLO thresholds and hysteresis. Use the procedure for the appropriate option to determine the
resistor values at the UVLO and OVLO pins.
• Choose the appropriate voltage, and pull-up resistor, for the Power Good output.
PC Board Guidelines
The following guidelines should be followed when designing the PC board for the LM5069:
• Place the LM5069 close to the board’s input connector to minimize trace inductance from the connector to the
FET.
• Place a small capacitor (1000 pF) directly adjacent to the VIN and GND pins of the LM5069 to help minimize
transients which may occur on the input supply line. Transients of several volts can easily occur when the
load current is shut off.
• The sense resistor (R
S
) should be close to the LM5069, and connected to it using the Kelvin techniques
shown in Figure 29.
• The high current path from the board’s input to the load (via Q1), and the return path, should be parallel and
close to each other to minimize loop inductance.
• The ground connection for the various components around the LM5069 should be connected directly to each
other, and to the LM5069’s GND pin, and then connected to the system ground at one point. Do not connect
the various component grounds to each other through the high current ground line.
• Provide adequate heat sinking for the series pass device (Q1) to help reduce stresses during turn-on and
turn-off.
• The board’s edge connector can be designed to shut off the LM5069 as the board is removed, before the
supply voltage is disconnected from the LM5069. In Figure 38 the voltage at the UVLO pin goes to ground
before V
SYS
is removed from the LM5069 due to the shorter edge connector pin. When the board is inserted
into the edge connector, the system voltage is applied to the LM5069’s VIN pin before the UVLO voltage is
taken high.
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