Datasheet

0
0
Drain Current
0
t1
0
0
t2
t3
a) Current Limit Only
V
SYS
V
DS
I
LIM
I
P
V
GATE
V
GSL
V
TH
t
ON
Source Voltage-toGate-
b) Power Limit and Current Limit
V
DS
Drain Current
t
ON
0
V
SYS
I
LIM
V
GATE
V
GSL
V
TH
t
ON
=
C
L
x V
SYS
2
2 x P
FET(LIM)
C
L
x P
FET(LIM)
2 x I
LIM
2
+
VIN
GND
PGD
OUT
Q1
GND
LM5069
V
SYS
C
L
R
L
R
S
VIN
GND
PGD
OUT
Q1
GND
LM5069
V
SYS
C
L
R
L
R
S
LM5069
SNVS452D –SEPTEMBER 2006–REVISED MAY 2013 www.ti.com
where R
L
is the load resistance. The Fault Timeout Period must be set longer than t
ON
to prevent a fault
shutdown before the turn-on sequence is complete.
Figure 30. No Load Current During Turn-On
Figure 31. Load Draws Current During Turn-On
B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (P
FET(LIM)
) is
defined by the resistor at the PWR pin, and the current sense resistor R
S
. See the Power Limit Threshold
section. If the current limit threshold (I
LIM
) is higher than the current defined by the power limit threshold at
maximum V
DS
(P
FET(LIM)/
V
SYS
) the circuit operates initially at the power limit mode when the V
DS
of Q1 is high,
and then transitions to current limit mode as the current increases to I
LIM
and V
DS
decreases. See Figure 32ab.
Assuming the load (R
L
) is not connected during turn-on, the time for the output voltage to reach its final value is
approximately equal to:
For example, if V
SYS
= 48V, C
L
= 1000 µF, I
LIM
= 1A, and P
FET(LIM)
= 20W, t
ON
calculates to ≊68 ms, and the initial
current level (I
P
) is approximately 0.42A. The Fault Timeout Period must be set longer than t
ON
.
Figure 32. MOSFET Power Up Waveforms
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