Datasheet

t
ON
= -(R
L
x C
L
) x In
(I
LIM
x R
L
) - V
SYS
(I
LIM
x R
L
)
t
ON
=
V
SYS
x C
L
I
LIM
SENSE
RESISTOR
R
S
FROM
SYSTEM
INPUT
VOLTAGE
TO MOSFET' S
DRAIN
HIGH CURRENT PATH
VIN
3
4
5
SENSE
9
8
7
6
LM5069
10
LM5069
www.ti.com SNVS452D –SEPTEMBER 2006–REVISED MAY 2013
Figure 29. Sense Resistor Connections
POWER LIMIT THRESHOLD
The LM5069 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the
current in R
S
), and the V
DS
of Q1 (SENSE to OUT pins). The resistor at the PWR pin (R
PWR
) sets the maximum
power dissipation for Q1, and is calculated from the following equation:
R
PWR
= 1.25 x 10
5
x R
S
x P
FET(LIM)
(2)
where P
FET(LIM)
is the desired power limit threshold for Q1, and R
S
is the current sense resistor described in the
Current Limit section. For example, if R
S
is 10 mΩ , and the desired power limit threshold is 60W, R
PWR
calculates to 75 kΩ. If Q1’s power dissipation reaches the threshold Q1’s gate is modulated to reduce the load
current, keeping Q1’s power from exceeding the threshold. For proper operation of the power limiting feature,
R
PWR
must be ≤150 kΩ. While the power limiting circuit is active, the fault timer is active as described in the Fault
Timer & Restart section. Typically, power limit is reached during startup, or if the output voltage falls due to a
severe overload or short circuit.
The programmed maximum power dissipation should have a reasonable margin from the maximum power
defined by the FET's SOA chart if the LM5069-2 is used since the FET will be repeatedly stressed during fault
restart cycles. The FET manufacturer should be consulted for guidelines.
If the application does not require use of the power limit function the PWR pin can be left open.
TURN-ON TIME
The output turn-on time depends on whether the LM5069 operates in current limit, or in both power limit and
current limit, during turn-on.
A) Turn-on with current limit only: The current limit threshold (I
LIM
) is determined by the current sense resistor
(R
S
). If the current limit threshold is less than the current defined by the power limit threshold at maximum V
DS
the circuit operates at the current limit threshold only during turn-on. Referring to Figure 32a, as the load current
reaches I
LIM
, the gate-to-source voltage is controlled at V
GSL
to maintain the current at I
LIM
. As the output voltage
reaches its final value (V
DS
≊ 0V) the drain current reduces to its normal operating value, and the gate is charged
to approximately 12V (V
GATE
). The time for the OUT pin voltage to transition from zero volts to V
SYS
is equal to:
where C
L
is the load capacitance. For example, if V
SYS
= 48V, C
L
= 1000 µF, and I
LIM
= 1A, t
ON
calculates to 48
ms. The maximum instantaneous power dissipated in the MOSFET is 48W. This calculation assumes the time
from t1 to t2 in Figure 32a is small compared to t
ON
, and the load does not draw any current until after the output
voltage has reached its final value, and PGD switches high (Figure 30). If the load draws current during the turn-
on sequence (Figure 31), the turn-on time is longer than the above calculation, and is approximately equal to:
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