Datasheet

I
LIMIT
Load
Current
GATE
Pin
TIMER
Pin
1 2 3 7 8
2 mA
pulldown
2. 5 P A
Fault Timeout
Period
0.3V
Fault
Detection
t
RESTART
1.25V
85
PA
4
V
16 PA
Gate Charge
Restart
Control
VIN
V
SYS
UVLO
OVLO
GND
R1
R2
R3
LM5069-1
LM5069
www.ti.com SNVS452D –SEPTEMBER 2006–REVISED MAY 2013
Fault Timer & Restart
When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either
limiting function is activated, an 85 µA fault timer current source charges the external capacitor (C
T
) at the
TIMER pin as shown in Figure 27 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout
Period before the TIMER pin reaches 4.0V, the LM5069 returns to the normal operating mode and C
T
is
discharged by the 2.5 µA current sink. If the TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is
switched off by a 2 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on
which version of the LM5069 is in use.
The LM5069-1 latches the GATE pin low at the end of the Fault Timeout Period. C
T
is then discharged to ground
by the 2.5 µA fault current sink. The GATE pin is held low by the 2 mA pull-down current until a power up
sequence is externally initiated by cycling the input voltage (V
SYS
), or momentarily pulling the UVLO pin below
2.5V with an open-collector or open-drain device as shown in Figure 26. The voltage at the TIMER pin must be
<0.3V for the restart procedure to be effective.
Figure 26. Latched Fault Restart Control
The LM5069-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 4.0V
and 1.25V seven times after the Fault Timeout Period, as shown in Figure 27. The period of each cycle is
determined by the 85 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor C
T
.
When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 16 µA current source at the GATE pin
turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart cycle repeat.
Figure 27. Restart Sequence (LM5069-2)
Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (V
SYS
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. Typically
the UVLO level at V
SYS
is set with a resistor divider (R1-R3) as shown in Figure 22. When V
SYS
is below the
UVLO level, the internal 21 µA current source at UVLO is enabled, the current source at OVLO is off, and Q1 is
held off by the 2 mA pull-down current at the GATE pin. As V
SYS
is increased, raising the voltage at UVLO above
2.5V, the 21 µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for
this threshold. With the UVLO pin above 2.5V, Q1 is switched on by the 16 µA current source at the GATE pin if
the insertion time delay has expired (Figure 24). See the Applications Section for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at V
SYS
can be set by
connecting the UVLO pin to VIN. In this case Q1 is enabled when the VIN voltage reaches the POR
EN
threshold.
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