Datasheet

TIMER
Pin
Load
Current
Output
Voltage
(OUT Pin)
PGD
UVLO
Normal Operation
GATE
Pin
Insertion Time
POR
IT
V
SYS
V
IN
I
LIMIT
16 PA source
2.5 PA
85
PA
1.25V
t 3
t 2t 1
In- rush
Limiting
5.5
PA
4V
1.5 mA
2 mA pull-down
230 mA
pull-down
LM5069
www.ti.com SNVS452D –SEPTEMBER 2006–REVISED MAY 2013
As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 24) an internal 85 µA fault timer current source charges C
T
.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the
TIMER pin reaches 4.0V the 85 µA current source is switched off, and C
T
is discharged by the internal 2.5 µA
current sink (t3 in Figure 24). The in-rush limiting interval is complete when the voltage at the OUT pin increases
to within 1.25V of the input voltage (V
SYS
), and the PGD pin switches high.
If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault
is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault
mode.
Figure 24. Power Up Sequence (Current Limit only)
Gate Control
A charge pump provides internal bias voltage above the output voltage (OUT pin) to enhance the N-Channel
MOSFET’s gate. The gate-to-source voltage is limited by an internal 12V zener diode. During normal operating
conditions (t3 in Figure 24) the gate of Q1 is held charged by an internal 16 µA current source to approximately
12V above OUT. If the maximum V
GS
rating of Q1 is less than 12V, a lower voltage external zener diode must be
added between the GATE and OUT pins. The external zener diode must have a forward current rating of at least
250 mA.
When the system voltage is initially applied, the GATE pin is held low by a 230 mA pull-down current. This helps
prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage
increases.
During the insertion time (t1 in Figure 24) the GATE pin is held low by a 2 mA pull-down current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO.
Following the insertion time, during t2 in Figure 24, the gate voltage of Q1 is modulated to keep the current or
power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the
TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 4V the
TIMER pin capacitor then discharges, and the circuit enters normal operation.
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