Datasheet

1 2 3 7 8
0.3V
Fault
Detection
I
LIMIT
t
RESTART
1.25V
4V
Fault Timeout
Period
Load
Current
GATE
Pin
TIMER
Pin
P
FET(LIM)
=
1.25 x 10
5
x R10
R9
www.ti.com Fault Detection and Restart
Power Limit
The maximum power dissipated in Q1 during turn-on, or due to a fault, is limited by R9 and R10 according
to the following equation:
(2)
With the components supplied on the evaluation board, P
FET(LIM)
= 45W. During turn-on, when the voltage
across Q1 is high, its gate is modulated to limit its drain current so the power dissipated in Q1 does not
exceed 45W. As the drain-to-source voltage decreases, the drain current increases, maintaining the power
dissipation constant. When the drain current reaches the current limit threshold set by R10 (5.5A), the
current is then maintained constant until the output voltage reaches its final value. The current then
decreases to a value determined by the load. See Figure 9 and Figure 10.
Each time Q1 is subjected to the maximum power limit conditions it is internally stressed for a few
milliseconds. For this reason, the power limit threshold must be set lower than the limit indicated by the
FET’s SOA chart. In this evaluation board, the power limit threshold is set at 45W, compared to ≊150W
limit indicated in the Vishay SUM40N15-38 data sheet. The FET manufacturer should be contacted for
more information on this subject.
Insertion Time
The insertion time starts when the input voltage at VIN reaches 7.6V, and its duration is equal to
t
INSERTION
= C8 x 7.24 x 10
5
(3)
During the insertion time, Q1 is held off regardless of the voltage at VIN. This delay allows ringing and
transients at VIN subside before the input voltage is applied to the load via Q1. The insertion time on this
evaluation board is ≊600 ms. See Figure 8.
7 Fault Detection and Restart
If the load current increases to the fault level (the current limit threshold, 5.5A), an internal current source
charges the timing capacitor at the TIMER pin. When the voltage at the TIMER pin reaches 4.0V, the fault
timeout period is complete, and the LM5069 shuts off Q1. The restart sequence then begins, consisting of
seven cycles at the TIMER pin between 4.0V and 1.25V, as shown in Figure 4. When the voltage at the
TIMER pin reaches 0.3V during the eighth high-to-low ramp, Q1 is turned on. If the fault is still present, the
fault timeout period and the restart sequence repeat.
Figure 4. Fault Timeout and Restart Sequence
The fault timeout period and the restart timing are determined by the TIMER capacitor according to the
following equations:
t
FAULT
= C8 x 4.7 x 10
4
(4)
t
RESTART
= C8 x 9.4 x 10
6
(5)
5
SNVA184B–September 2006–Revised May 2013 AN-1522 LM5069 Evaluation Board
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