Datasheet

UVLO
OVLO
R1
R2
R3
R4
PGD
V
PGD
TIMER PWR
GND
R7
R8
0:
C6
Open
C8
R9
8
576
4
3
VIN SENSE GATE
OUT
SUM 40N15-
38
Q1
PGD
GND
OUT
C1
100V
Z1
R10
GND
2 1
10
9
1
2
3
JMP2
1
2 3
JMP1
C7
100 PF
BACKPLANE
HOT SWAP CIRCUIT
J2
LOAD
J1
SW1
+9V to +78V
200V
0.
01:
C5
0.1 PF
100V
C3
100 PF
200V
C4
100 PF
200V
TP1
95.3k
100k
P1
LM5069
56k
P0.82 F
70V
3.32k
4.64k
N/U
V
IN
0.001
Board Configuration www.ti.com
to the right of the vertical dashed line is the hot swap circuit. The system voltage is to be connected to the
input terminal block (J1). The external load is to be connected to the output terminal block (J2). Capacitors
C3 and C4 represent capacitance which is typically present on the input of the load circuit, and are
present on this evaluation board so the turn-on characteristics of the LM5069 may be tested without
having to connect a load.
For a hot swap circuit to function reliably, capacitance is needed on the supply side of the system
connector (C7). Its purpose is to minimize voltage transients which occur whenever the load current
changes or is shut off. If the capacitance is not present, wiring inductance in the supply lines generate a
voltage transient at shutoff which can exceed the absolute maximum rating of the LM5069, resulting in its
destruction.
The LM5069EVB is supplied with pins 2-3 jumpered on JMP1, and pins 1-2 jumpered on JMP2.
Figure 2. Evaluation Board Schematic
2
AN-1522 LM5069 Evaluation Board SNVA184B–September 2006–Revised May 2013
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