Datasheet
LM5068
www.ti.com
SNVS254C –JANUARY 2004–REVISED MARCH 2013
PIN DESCRIPTION
PIN NAME DESCRIPTION APPLICATION INFORMATION
1 PWRGD Open Drain Power Good indicator Following a successful power-up sequence the PWRGD
signal will be active. The LM5068-1 and -2 are configured
for an active power-good state as HIGH, while the
LM5068-3 and –4 are configured for an active power-good
state as LOW.
2 OV Line Over-Voltage Shutdown An external resistor divider from the power source sets the
over-voltage shutdown level. Hysteresis is generated by an
internal current source which sources 20 µA into the
external divider when the OV pin exceeds 2.5V.
3 UV Line Under-Voltage Shutdown An external resistor divider from the power source sets the
under-voltage shutdown level. Hysteresis is set by an
internal current source which sinks 20 µA from the external
divider when the UV pin falls below 2.5V.
4 V
EE
Negative Supply Voltage Input
5 SENSE Current Sense Input Load current is monitored via an external current sense
resistor (R
s
). If the voltage across R
s
exceeds 50mV the
fault timer is initiated. Load current is actively limited to
100mV/R
s
. If the sense voltage exceeds 200mV due to a
catastrophic fault, the fast gate pull down circuit will reduce
the MOSFET gate voltage and initiate active current
limiting.
6 GATE N-Channel MOSFET Gate Drive Output This output is pulled high by a 60 µA current source to turn
on the MOSFET.
7 TIMER Timer Input An external capacitor connected to this pin sets the initial
start-up delay and the delay to shutdown in the event of an
over-current condition. This pin is also used for the
automatic re-try timing sequence, following fault shutdown
(-2 and –4 versions).
8 V
DD
Positive Supply Voltage Input
Configuration Table
Part Number Latch Off /Successive Re-try Power Good Polarity Package
LM5068MM-1/MMX-1 Latch Off Active HIGH VSSOP- 8
LM5068MM-2/MMX-2 Auto Re-try Active HIGH
LM5068MM-3/MMX-3 Latch Off Active LOW
LM5068MM-4/MMX-4 Auto Re-try Active LOW
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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