Datasheet

TIMER
GATE
DRAIN
SENSE
PWRGD
Normal Mode
Fast Gate
Pull Down
1 2
V
CB
V
AC
V
FDC
V
THVT
V
TLVT
LM5068
www.ti.com SNVS254C –JANUARY 2004–REVISED MARCH 2013
Figure 31 shows analog current limit behavior when the SENSE pin voltage exceeds V
AC
for a period of time,
which activates the Analog Current Limit but never reaches the fault timer threshold. At that time the GATE is
regulated by the analog current limit amplifier loop. When the SENSE voltage falls below V
AC
, GATE is allowed
to charge with a 60µA current source. A compensation circuit consisting of a resistor and a capacitor in series,
connected between GATE and V
EE
stabilizes the current limit loop.
Figure 32. Fast Current Limit Fault
In case of a severe fault (for example sudden short-circuit of the output load) the SENSE pin exceeds the V
FDC
threshold and GATE immediately pulls down until the Active Current Limit loop establishes control of the current
in the MOSFET. Careful selection of TIMER capacitor and MOSFET with adequate current and voltage ratings
will prevent damage to MOSFET low impedance faults.
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