Datasheet

SENSE
GATE
TIMER
OV
6 PA
V
CB
V
AC
PWRGD
V
THVT
V
G
OV LOW
OV HIGH
4 5
6 7
1 2
3
60 PA
60 PA
230 PA
OV PIN OVERSHOOTS OV HIGH, GATE IS
PULLED DOWN. PGOOD IS PULLED
LOW AND TIMER IS UNAFFECTED
OV DROPS BELOW OV LOW, GATE STARTS
RAMPING UP AND PGOOD BECOMES HIGH
WHEN GATE VOLTAGE REACHES V
G
LM5068
www.ti.com SNVS254C –JANUARY 2004–REVISED MARCH 2013
Figure 29. Over-Voltage Timing Behavior
During normal operation, if the OV pin exceeds OV HIGH, as shown at time point 1 in the above diagram, the
TIMER status is unaffected. The GATE and PWRGD ( for LM5068-1 & -2) pins are pulled low and the load is
disconnected. At time point 2, OV recovers and drops below the OV LOW threshold, the GATE start-up cycle
begins. If the load capacitor is completely depleted during OV conditions, a full start-up cycle is initiated.
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