Datasheet

UV
UV LOW
UV HIGH
TIMER
6 PA
GATE
SENSE
PWRGD
DRAIN
V
THVT
V
TLVT
V
CB
V
AC
6 PA
4
10
INITIAL TIMING
GATE
RAMP-UP
60 PA
5 6 7
8 9
11
1
2
3
240 PA
60 PA
UV DROPS BELOW UV HIGH, GATE
AND TIMER ARE PULLED DOWN
UV CLEARS UV LOW, TIMER RAMPS
UP PROVIDED ALL INTERLOCK
CONDITIONS ARE MET
TIMER CLEARS V
TLVT
. GATE
VOLTAGE RAMPS UP
LM5068
SNVS254C –JANUARY 2004–REVISED MARCH 2013 www.ti.com
Assuming all of the initial conditions are met, the power-up sequence starts with Timer capacitor (C
T
) getting
charged. C
T
is charged with 6µA current source up to V
THVT
(4V) then quickly discharge to V
TLVT
(1V). At time
point (2) the 60µA GATE current source is enabled. The GATE voltage increases until the MOSFET starts
conducting causing the SENSE voltage to increase until Active Current Limiting is activated (3). During the
current limiting period (3-4), C
T
is charged again, but there is not enough time to reach the 4V threshold before
the load capacitor is fully charged and the SENSE voltage falls below V
CB
. The GATE continues to fully enhance
the MOSFET and activating the PWRGD when the GATE voltage exceeds 8V (see Figure 27).
Figure 28. Under-Voltage Timing Behavior
UV drops below UV HIGH (time point 1) puts the controller into a disabled mode. Later, UV increases over the
UV LOW threshold (time point 3), which initiates a system power-up sequence.
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