Datasheet

TIMER
GATE
DRAIN
SENSE
PWRGD
Gate Ramp-up
Initial Timing
1 3 4 5
6
V
THVT
V
TLVT
V
CB
V
AC
6PA
60PA
Normal Mode
Current Limit
2
7
6PA
V
EE
PIN SENSE PIN
TO SOURCE
OF MOSFET
TO NEGATIVE
TERMINAL
OF
POWER
SOURCE
SENSE
RESISTOR
HIGH CURRENT PATH
LM5068
UV PIN
GATE PIN
LM5068
www.ti.com SNVS254C –JANUARY 2004–REVISED MARCH 2013
The N-channel MOSFET selection for use with the LM5068 controller in this example must be capable of
sustaining V
DD
=100V and I
(MAX)
=3A for 7.5ms in the worst case fault condition. A device that meets the
established criteria is the Vishay - 5UB85N10-10.
External Sense Resistor
Precise current measurement depends on the accuracy of the sense resistor (R
S
). For the optimal results, Kelvin
connection and close location of R
S
to the LM5068 should be considered. Figure 26 demonstrates PCB layout for
the Kelvin sensing.
The R
S
power rating should be greater than I
2
L
*
R, where I
L
is the normal maximum operating load.
Figure 26. Sense Resistor Connections
Timing Diagrams
Figure 27. System Power-Up Timing Behavior
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