Datasheet

LM5068
www.ti.com
SNVS254C JANUARY 2004REVISED MARCH 2013
Latch-Off and Auto-Retry
If the fault conditions persist long enough for TIMER to charge C
T
to 4V, the LM5068 latches off (LM5068-1, -3)
or switches off and initiates the re-try timer (LM5068-2, -4).
At the fault condition, after reaching the 4V, the TIMER pin will continue to ramp-up with A current source until
it reaches the internal regulated voltage, which is equivalent to the saturation GATE drive voltage. The LM5068-1
and LM5068-3 remains off until the controller is reset by either temporarily pulling the UV pin low, pulling the
TIMER pin below 1 volt, or decreasing the input voltage below the internal V
DD
under-voltage lockout (UVLO)
threshold.
The LM5068-2 and LM5068-4 respond to a fault condition by pulling the GATE and TIMER pins low and then
initiating a timer sequence for automatic re-try. The re-try timer sequence begins with C
T
capacitor being charged
slowly to 4V with a A current source and then discharged quickly to 1V with a 30mA discharge current. After 8
charge/discharge cycles the GATE pin is released and charged with a 60µA current source. If the fault condition
persists, the LM5068 will again turn off the MOSFET and another 8-cycle fault timer sequence will begin.
Power Good Flag
The power good flag (PWRGD) is activated when the MOSFET GATE is fully enhanced (>8V) and the voltage
input UV and OV comparators are satisfied. The power good output is a 90V capable open drain N-Channel
MOSFET. The LM5068-1 and LM5068-2 provide an active HIGH power-good state, while the LM5068-3 and
LM5068–4 are configured for an active LOW power-good state. The UV comparator, OV comparator, V
DD
UVLO,
or a circuit breaker time-out will reset the power good flag.
Internal Soft-Start
An internal soft-start feature ramps the (positive) input of the analog current limit amplifier during initial start-up.
The ramp duration is approximately 200µs. This feature reduces the load current slew rate (di/dt) at start-up.
Design Information
The LM5068 contains an internal regulator enabling the V
DD
pin to be connected directly to the line voltage from
10 to 90V. A local RC filter (0.1µF ceramic capacitor and 499 resistor) connected between V
DD
and V
EE
is
recommended to filter supply transients that exceed the 100V Absolute Maximum Rating.
UV and OV Thresholds and Voltage Divider Selection for R1, R2, and R3
Two comparators detect under-voltage and over-voltage conditions at the UV and OV pins. The threshold
voltages (V
UV
, V
OV
) of the UV and OV comparators are nominally 2.5V. Hysteresis is accomplished by 20µA
current sources (I
UVHCS
), into the external resistor divider connected to the UV and OV pins as shown in
Figure 25
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