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LM5068

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SNVS254C –JANUARY 2004–REVISED MARCH 2013

LM5068 Negative Voltage Hot Swap Controller

Check for Samples: LM5068

FEATURES

DESCRIPTION

The LM5068 hot-swap controller provides intelligent

• Safe Module Insertion and Removal from Live

control of power supply connections during the

Backplanes

insertion and removal of circuit cards powered by live

• In-Rush Current Limiting for Safe Board

system backplanes.

Insertion into Live Backplanes

The LM5068 provides both in-rush current control and

• Fast Response to Over-Current Fault

short-circuit protection functions, and limits power

Conditions with Active Current Limiting

supply transients in the backplane caused by the

• -10V to -90V Input Range

insertion of additional circuit cards. The LM5068

controls the external N-Channel MOSFET to provide

• Programmable Under-Voltage/Over-Voltage

programmable load current limiting and circuit

Shutdown Protection with Adjustable

breaker functions using a single external current

Hysteresis

sense resistor. The LM5068 issues a power good

• Programmable Multi-Function Timer for Board

(PWRGD) signal at the conclusion of a successful

Insertion De-Bounce Delay

power-on sequence. Input over-voltage or under -

voltage fault conditions will cancel the PWRGD

• Fault Timer Avoids Nuisance Trips Caused by

indication.

Short Duration Load Transients

• Active Gate Clamping During Initial Power

The LM5068-1 and -2 indicate power-good as an

open-drain active HIGH PWRGD state. The LM5068-

Application

3 and -4 indicate power-good as an open-drain active

• Available in both Latched Fault and Automatic

LOW PWRGD state. The LM5068-1 and -3 latch off

Re-Try Versions

after a fault condition is detected while the LM5068-2

• Available with either Active HIGH or Active

and -4 continuously re-try at intervals set by a

LOW Power Good Flag

programmable timer.

The LM5068 is available in a VSSOP-8 package.

APPLICATIONS

• - 48V Power Modules

• Central Office Switching

• Distributed Power Systems

• Electronic Circuit Breaker

• PBX Systems

• Negative Power Supply Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 LM5068 Negative Voltage Hot Swap Controller Check for Samples: LM5068 FEATURES DESCRIPTION • The LM5068 hot-swap controller provides intelligent control of power supply connections during the insertion and removal of circuit cards powered by live system backplanes.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Typical Application VDD (GND) RF 499: ENABLE R1 100 k: 1% CF + 0.1 PF + PWRGD VDD CL 100 PF UV R2 5.5 k: 1% LOAD LM5068 OV VEE TIMER R3 4.5 k: 1% CT 0.22 PF Cc 22 nF Rs 12 m: VEE (-48V) GATE + + SENSE Q1 SUB85N10-10 Figure 1.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 PIN DESCRIPTION PIN NAME 1 PWRGD 2 3 DESCRIPTION APPLICATION INFORMATION Open Drain Power Good indicator Following a successful power-up sequence the PWRGD signal will be active. The LM5068-1 and -2 are configured for an active power-good state as HIGH, while the LM5068-3 and –4 are configured for an active power-good state as LOW.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) VDD (VDD to VEE) 100V PWRGD (PWRGD to VEE) 100V SENSE (SENSE to VEE) 8V UV/OV (Clamped) (UV/OV to VEE) 8V All Other Inputs to VEE 16V Junction Temperature (TJ) +150°C Storage Temperature (TS) -55°C to +150°C Soldering Information ESD Rating (1) (2) (3) (3) 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Electrical Characteristics (continued) Specifications in standard typeface are for TJ = +25°C, and those in boldface type apply over the full operating junction temperature range. Unless otherwise noted VDD − VEE = 48V.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Block Diagram VREG + SERIES REGULATOR VDD UV HYSTERESIS CS 0.5V 20PA 2.5V + - UV 60PA OV + 2.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Typical Performance Characteristics IIN vs Temperature IIN vs VDD 1.2 0.801 VDD = 90V -40oC 0.701 1.1 0.601 1 -25oC IIN (mA) IIN (mA) 0.501 0.9 VDD = 48V 125oC 0.401 0.301 0.8 0.201 0.7 0.101 0.6 -40 0.001 -25 0 25 50 75 105 0 2 4 6 8 VDD (V) TEMPERATURE (oC) Figure 2. Figure 3. VDD Under-Voltage Shutdown (VUVS) vs Temperature VDD Under-Voltage Shutdown Hysteresis (VUVSH) vs Temperature 8.6 0.8 8.55 0.75 8.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Over-Voltage Comparator Threshold Hysteresis Current Sink (IOVHCS) vs Temperature 1400 21 1200 tUVCD (ns) / tOVCD(ns) 21.5 20.5 IOVHCS (PA) UV Comparator Delay (tUVCD) and OV Comparator Delay (tOVCD) vs Temperature 20 19.5 tUVCD 1000 800 600 tOVCD 19 18.5 -40 400 -25 0 25 50 75 200 -40 105 -25 0 25 50 75 105 TEMPERATURE (oC) TEMPERATURE (oC) Figure 8. Figure 9.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Timer On (Initial Cycle, Sourcing) vs Temperature 1.2 7.5 1.16 7.0 1.12 6.5 ITIMER (PA) VTLVT (V) Timer Low Voltage Threshold (VTLVT) vs Temperature 1.08 6.0 1.04 5.5 1.0 5.0 0.96 -40 -25 0 25 50 75 4.5 -40 105 -25 0 25 50 75 105 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 14. Figure 15.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) PWRGD Low Voltage (VPGLV) vs Temperature 75 0.35 70 0.3 65 0.25 VPGLV (V) IGATE (PA) Gate Pin Current (Sourcing) (IGATE) vs Temperature 60 0.2 55 0.15 50 0.1 45 -40 -25 0 25 50 75 ISINK = 1mA 0.05 -40 105 25 0 25 50 TEMPERATURE ( C) TEMPERATURE (oC) Figure 20. Figure 21. o 75 105 Gate Voltage at onset of PWRGD (VPGV) vs Temperature 8.1 8.05 8.0 VPGV (V) 7.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 FUNCTION DESCRIPTION The LM5068 is designed to facilitate the insertion and removal of circuit cards into live backplanes in a controlled manner. Because the supply bypass capacitors on the circuit card can draw large transient currents, it is critical to control the supply current during insertion to limit system power glitches and connector damage.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Over and Under-Voltage Lockout The line Under-voltage lockout (UVLO) circuitry of the LM5068 monitors VDD for under-voltage conditions, where VUVS is the negative going threshold and the hysteresis is VUVSH (see Electrical Characteristics). A VDD - VEE voltage less than 8.5V (VUVS) keeps the controller in a disabled mode. Raising the VDD voltage above 9.1V (VUVS + VUVSH) releases the VDD UVLO and enables the controller.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Latch-Off and Auto-Retry If the fault conditions persist long enough for TIMER to charge CT to 4V, the LM5068 latches off (LM5068-1, -3) or switches off and initiates the re-try timer (LM5068-2, -4). At the fault condition, after reaching the 4V, the TIMER pin will continue to ramp-up with 6µA current source until it reaches the internal regulated voltage, which is equivalent to the saturation GATE drive voltage.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Vsupply www.ti.com UV HYSTERESIS CS RF VDD 20PA R1 CF + 2.5V + UV R2 OV + 2.5V R3 20PA VEE OV HYSTERESIS CS LM5068 Figure 25. UV/OV Setting Hysteresis is necessary to prevent a possible “chattering” condition when the controller enables or disables the external MOSFET. The change in line current interacts with the line impedance. This interaction can cause several rapid on/off cycles on the MOSFET.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 The typical operating ranges of under-voltage and over-voltage thresholds are calculated from the above equations with known resistors. For example, for resistor values: R1=130KΩ, R2=5.5KΩ, and R3=4.5KΩ, the computed thresholds are: • UV turn-on = 37.60V • UV turn-off = 35.0V • OV turn-off = 77.78V • OV turn-on = 75.07V To maintain the threshold's accuracy, a resistor tolerance of 1% or better is recommended.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Sense Resistor (Rs), Timer Capacitor (CT) and N-Channel Mosfet (Q1) Selection To select the proper MOSFET, the following safe operating area (SOA) parameters are needed: maximum input voltage, maximum current and the maximum current conduction time.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 The N-channel MOSFET selection for use with the LM5068 controller in this example must be capable of sustaining VDD=100V and I(MAX)=3A for 7.5ms in the worst case fault condition. A device that meets the established criteria is the Vishay - 5UB85N10-10. External Sense Resistor Precise current measurement depends on the accuracy of the sense resistor (RS).
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Assuming all of the initial conditions are met, the power-up sequence starts with Timer capacitor (CT) getting charged. CT is charged with 6µA current source up to VTHVT (4V) then quickly discharge to VTLVT (1V). At time point (2) the 60µA GATE current source is enabled. The GATE voltage increases until the MOSFET starts conducting causing the SENSE voltage to increase until Active Current Limiting is activated (3).
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 OV PIN OVERSHOOTS OV HIGH, GATE IS PULLED DOWN. PGOOD IS PULLED LOW AND TIMER IS UNAFFECTED 1 2 OV DROPS BELOW OV LOW, GATE STARTS RAMPING UP AND PGOOD BECOMES HIGH WHEN GATE VOLTAGE REACHES VG 3 4 5 6 7 OV LOW OV HIGH OV VTHVT 230 PA 6 PA TIMER GATE 60 PA VG 60 PA VAC VCB SENSE PWRGD Figure 29.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 www.ti.com Normal Mode 1 2 VTHVT 240PA TIMER VTLVT GATE DRAIN VAC VCB SENSE PGOOD Circuit Breaker Limit Figure 30. Circuit Breaker Current Limit Fault The above timing waveform shows the circuit breaker current limit fault behavior. The timer capacitor is charged with 240µA when the SENSE pin exceeds VCB. If the SENSE pin drops below VCB before the TIMER reaches VTHVT, the timer capacitor will be discharged with 6µA.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Figure 31 shows analog current limit behavior when the SENSE pin voltage exceeds VAC for a period of time, which activates the Analog Current Limit but never reaches the fault timer threshold. At that time the GATE is regulated by the analog current limit amplifier loop. When the SENSE voltage falls below VAC, GATE is allowed to charge with a 60µA current source.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Normal Mode www.ti.com 1 2 Circuit Breaker Timeout Mode 3 4 5 6 7 Normal Mode VTHVT 240PA 6PA TIMER 6PA VTLVT 30mA 60PA GATE DRAIN VAC VCB SENSE PWRGD Circuit Breaker Limit Gate Ramp-up Figure 33. Shutdown Cooling Timing Behavior Figure 33 shows the timer behavior for LM5068-2, -4 during fault re-try time. During normal operation, whenever the SENSE pin exceeds the 50mV, circuit breaker fault limit, the timer capacitor begins to charge.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 Evaluation Board Schematic GND GND J1 J2 -48V TP8 UV/OV TP1 VDD R10 499: R1 0: R5 100k: + C5 100PF + -48V C6 0.1PF TP4 UV R2 100k: VEE U1 TP5 OV R3 4.02k: VDD 8 OV TIMER 7 3 UV GATE 6 4 VEE SENSE 5 1 PWRGD 2 TP6 TIMER + R4 3.40k: C2 NOT USED + R9 0: + TP7 GATE LM5068 C1 NOT USED C4 0.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 PART VALUE C1 NOT USED 24 www.ti.com PACKAGE DESCRIPTION PART NUMBER C2 NOT USED C3 0.022uF/ 50V C0805 CAPACITOR, CERAMIC,KEMET C0805C223K5RAC C4 0.33uF / 50V C0805 CAPACITOR,CERAMIC,KEMET C0805C334K5RAC C5 100uF / 100V CAPACITOR, ALUMINIUM ELECTROLYTIC, SURFACE MOUNT,PANASONIC EEV-FK2A101M C6 0.
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LM5068 www.ti.
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LM5068 SNVS254C – JANUARY 2004 – REVISED MARCH 2013 26 www.ti.
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LM5068 www.ti.com SNVS254C – JANUARY 2004 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5068MM-1/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5068MM-2 VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5068MM-2/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5068MM-1/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MM-2 VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MM-2/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MM-3/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MM-4/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM5068MMX-1/NOPB VSSOP DGK 8 3500 367.0 367.
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