Datasheet
LM5067
SNVS532C –OCTOBER 2007–REVISED MARCH 2013
www.ti.com
Electrical Characteristics (continued)
Limits in standard type are for T
J
= 25°C only; limits in boldface type apply over the junction temperature (T
J
) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at T
J
= 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: I
CC
= 2 mA, OUT Pin = 48V above VEE, all voltages are with respect to VEE. See
(1)
.
Symbol Parameter Conditions Min Typ Max Unit
OVLO
DEL
OVLO delay Delay to GATE high 26 µs
Delay to GATE low 12 µs
OVLO
BIAS
OVLO bias current OVLO = VEE + 2.4V 1 µA
Gate Control (GATE Pin)
I
GATE
Source current Normal Operation -72 -52 -32 µA
Sink current UVLO < 2.5V 1.9 2.2 2.68 mA
SENSE - VEE =150 mV or 45 110 200
VCC - VEE < POR
IT
, V
GATE
= 5V
V
GATE
Gate output voltage in normal operation GATE-VEE voltage V
Z
V
Current Limit
V
CL
Threshold voltage SENSE - VEE voltage 44 50 56 mV
t
CL
Response time SENSE - VEE stepped from 0 mV 25 µs
to 80 mV
Circuit Breaker
V
CB
Threshold voltage SENSE - VEE voltage 70 100 130 mV
t
CB
Response time SENSE - VEE stepped from 0 mV 0.65 1.0 µs
to 150 mV, time to GATE low, no
load
Power Limit (PWR Pin)
PWR
LIM
Power limit sense voltage (SENSE - VEE) OUT - SENSE = 24V, R
PWR
= 75 16.5 22 27.5 mV
kΩ
I
PWR
PWR pin current V
PWR
= 2.5V -23 µA
Timer (TIMER Pin)
V
TMRH
Upper threshold 3.76 4 4.16 V
V
TMRL
Lower threshold Restart cycles (LM5067-2) 1.18 1.25 1.32 V
End of 8th cycle (LM5067-2) 0.3 V
Re-enable threshold (LM5067-1) 0.3 V
I
TIMER
Insertion time current TIMER pin = 2V -9.5 -6 -2.5 µA
Sink current, end of insertion time TIMER pin = 2V 1.2 1.55 1.9 mA
Fault detection current TIMER pin = 2V -140 -85 -44 µA
Sink current, end of fault time 0.9 2.5 4.25 µA
DC
FAULT
Fault Restart Duty Cycle LM5067-2 0.5 %
t
FAULT
Fault to GATE low delay TIMER pin reaches 4.0V 15 µs
Power Good (PGD Pin)
PGD
TH
Threshold measured at OUT - SENSE Decreasing 1.16 1.23 1.28 V
2 5
Increasing, relative to decreasing 1.14 1.25 1.32
threshold 3 5
PGD
VOL
Output low voltage I
SINK
= 2 mA 60 150 mV
PGD
IOH
Off leakage current V
PGD
= 80V 5 µA
Thermal Resistance
(2)
θ
JA
Junction to Ambient VSSOP package 94 °C/W
θ
JC
Junction to Case VSSOP package 44 °C/W
θ
JA
Junction to Ambient SOIC-14 Package 90 °C/W
(2) Tested on a 4 layer JEDEC board with 2 vias under the package. See JEDEC standards JESD51-7 and JESD51-3. See the Thermal
Considerations section.
4 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM5067