Datasheet

VEE
PGD
Power
Good
LM5067
PGD
Power
Good
LM5067
PGD
Power
Good
LM5067
R
PG2
a) Delay Rising Edge Only
b) Long delay at rising edge,
Short delay at falling edge
c) Short Delay at Rising Edge and Long
VEE
VEE
C
PG
C
PG
R
PG1
R
PG2
V
SYS
C
PG
V
PGD
V
PGD
R
PG
V
SYS
Delay at Falling Edge
,
or Equal Delays
V
SYS
V
PGD
R
PG1
LM5067
www.ti.com SNVS532C –OCTOBER 2007–REVISED MARCH 2013
Figure 20. Adding Delay to the Power Good Output Pin
Design-in Procedure
The recommended design-in procedure for the LM5067 is as follows:
• Determine the minimum and maximum system voltages (VEE). Select the input resistor (R
IN
) to provide at
least 2 mA into the VCC pin at the minimum system voltage.The resistor’s power rating must be suitable for
its power dissipation at maximum system voltage ((V
SYS
– 13V)
2
/R
IN
).
• Determine the current limit threshold (I
LIM
). This threshold must be higher than the normal maximum load
current, allowing for tolerances in the current sense resistor value and the LM5067 Current Limit threshold
voltage. Use equation 1 to determine the value for R
S
.
• Determine the maximum allowable power dissipation for the series pass FET (Q1), using the device’s SOA
information. Use equation 2 to determine the value for R
PWR
.
• Determine the value for the timing capacitor at the TIMER pin (C
T
) using equation 3. The fault timeout
period (t
FAULT
) must be longer than the circuit’s turn-on-time. The turn-on time can be estimated using
the equations in the Turn-on Time section of this data sheet, but should be verified experimentally. Allow for
tolerances in the values of the external capacitors, sense resistor, and the LM5067 Electrical Characteristics
for the TIMER pin, current limit and power limt. Review the resulting insertion time, and the restart timing if
the LM5067-2 is used.
• Choose option A, B, C, or D from the UVLO, OVLO section of the Application Information for setting the
UVLO and OVLO thresholds and hysteresis. Use the procedure in the appropriate option to determine the
resistor values at the UVLO and OVLO pins.
• Choose the appropriate voltage, and pull-up resistor, for the Power Good output.
PC Board Guidelines
The following guidelines should be followed when designing the PC board for the LM5067:
• Place the LM5067 close to the board’s input connector to minimize trace inductance from the connector to the
FET.
• Place R
IN
and C
IN
close to the VCC and VEE pins to keep transients below the Absolute Maximum rating of
the LM5067. Transients of several volts can easily occur when the load current is shut off.
• The sense resistor (R
S
) should be close to the LM5067, and connected to it using the Kelvin techniques
shown in Figure 10.
• The high current path from the board’s input to the load, and the return path (via Q1), should be parallel and
close to each other wherever possible to minimize loop inductance.
• The VEE connection for the various components around the LM5067 should be connected directly to each
other, and to the LM5067’s VEE pin, and then connected to the system VEE at one point. Do not connect the
various components to each other through the high current VEE track.
• Provide adequate heat sinking for the series pass device (Q1) to help reduce thermal stresses during turn-on
and turn-off.
• The board’s edge connector can be designed to shut off the LM5067 as the board is removed, before the
supply voltage is disconnected from the LM5067. In Figure 21 the voltage at the UVLO/EN pin goes to VEE
before V
SYS
is removed from the LM5067 due to the shorter edge connector pin. When the board is inserted
into the edge connector, the system voltage is applied to the LM5067’s VEE and VCC pins before voltage is
applied to the UVLO/EN pin.
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