Datasheet

V
PGD
Power
Good
LM5067
VEE
C
IN
V
SYS
R
IN
VEE
PGD
GND
R
PG
VCC
Shutdown
Control
VCC
OVLO
VEE
System Gnd
VEE
SENSE
V
SYS
C
IN
R
IN
R1
R2
R
S
UVLO/EN
LM5067
R3
Shutdown
Control
VCC
OVLO
VEE
System Gnd
VEE
SENSE
V
SYS
C
IN
R
IN
R3
100k
R1
R2
R
S
UVLO/EN
LM5067
LM5067
SNVS532C –OCTOBER 2007–REVISED MARCH 2013 www.ti.com
SHUTDOWN / ENABLE CONTROL
Figure 17 shows how to use the UVLO/EN pin for remote shutdown and enable control. Taking the UVLO/EN pin
below its 2.5V threshold (with respect to VEE) shuts off the load current. Upon releasing the UVLO/EN pin the
LM5067 switches on the load current with in-rush current and power limiting. In Figure 18 the OVLO pin is used
for remote shutdown and enable control. When the external transistor is off, the OVLO pin is above its 2.5V
threshold (with respect to VEE) and the load current is shut off. Turning on the external transistor allows the
LM5067 to switch on the load current with in-rush current and power limiting.
Figure 17. a) Shutdown/Enable Using the UVLO/EN Figure 18. b) Shutdown/Enable Using the OVLO
Pin Pin
POWER GOOD PIN
During initial power up, the Power Good pin (PGD) is high until the operating voltage (VCC – VEE) increases
above ≊2V. PGD then switches low, remaining low as the system voltage and the operating voltage increase.
After Q1 is switched on, when the voltage at the OUT pin is within 1.23V of the SENSE pin (Q1’s V
DS
<1.23V),
PGD switches high indicating the output voltage is at, or nearly at, its final value. Any of the following situations
will cause PGD to switch low within ≊10 µs:
• The V
DS
of Q1 increases above 2.5V.
• The system input voltage decreases below the UVLO level.
• The system input voltage increase above the OVLO level.
• The TIMER pin increases to 4V due to a fault condition.
A pull-up resistor is required at PGD as shown in Figure 19. The pull-up voltage (V
PGD
) can be as high as 80V
above VEE, with transient capability to 100V, and can be higher or lower than the system ground.
Figure 19. Power Good Output
If a delay is required at PGD, suggested circuits are shown in Figure 20. In Figure 20a, capacitor C
PG
adds delay
to the rising edge, but not to the falling edge. In Figure 20b, the rising edge is delayed by R
PG1
+ R
PG2
and C
PG
,
while the falling edge is delayed a lesser amount by R
PG2
and C
PG
. Adding a diode across R
PG2
. Figure 20c
allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.
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