Datasheet

50k
OVLO
VEE
TIMER AND GATE
LOGIC CONTROL
GND
VEE
To Load
Vee
R4
LM5067
22 PA
C
IN
R
IN
V
SYS
R1
R3
UVLO/EN
2.5V
2.5V
22 PA
VCC
V
UVH
= 2.5V + [R1 x (2.5V + 22 PA)]
R2
V
UVL
=
2.5V x (R1 + R2)
R2
V
OVH
=
2.5V x (R3 + R4)
R4
V
OVL
= 2.5V + [R3 x (2.5V - 22 PA)]
R4
V
OV(HYS)
= R3 x 22 PA
V
UV(HYS)
= R1 x 22 PA
LM5067
www.ti.com SNVS532C –OCTOBER 2007–REVISED MARCH 2013
(16)
NOTE
Ensure the voltages at the UVLO and OVLO pins do not exceed the Absolute Maximum
ratings for those pins when the system voltage is at maximum.
Option C: The minimum UVLO level is obtained by connecting the UVLO pin to VCC as shown in Figure 16. Q1
is switched on when the operating voltage reaches the POR
EN
threshold (≊8.4V). The OVLO thresholds are set
by R3 and R4 using the procedure in Option B.
NOTE
Ensure the voltage at the OVLO pin does not exceed the Absolute Maximum ratings for
that pin when the system voltage is at maximum.
Figure 16. UVLO = POR
EN
Option D: The OVLO function can be disabled by connecting the OVLO pin to VEE. The UVLO thresholds are
set as described in Option B or Option C.
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