Datasheet

1
2
3
4
5
11
10
9
8
7
6
UVLO/EN
OVLO
PWR
VEE
VCC
12
13
14
N/C
N/C
OUT
N/C
GATE
SENSE
PGD
TIMER
N/C
1
2
3
4
5
10
9
8
7
6
UVLO/EN
OVLO
PWR
VEE TIMER
PGD
OUT
VCC
GATE
SENSE
LM5067
SNVS532C –OCTOBER 2007–REVISED MARCH 2013 www.ti.com
Connection Diagram
NOTE: N/C Pins are internally not connected to anything.
Figure 2. Top View Figure 3. Top View
10-Lead VSSOP 14-Lead SOIC
PIN DESCRIPTIONS
Pin No.
Name Description Applications Information
VSSOP-10 SOIC-14
1 1 VCC Positive supply Connect to system ground through a resistor. Connect a bypass capacitor to
input VEE. The voltage from VCC to VEE is nominally 13V set by an internal zener
diode.
2 3 UVLO/EN Under-voltage An external resistor divider from the system input voltage sets the under-voltage
lockout turn-on threshold. The enable threshold at the pin is 2.5V above VEE. An internal
22 µA current source provides hysteresis. This pin can be used for remote enable
and disable.
3 4 OVLO Over-voltage An external resistor divider from the system input voltage sets the over-voltage
lockout turn-off threshold. The disable threshold at the pin is 2.5V above VEE. An internal
22 µA current source provides hysteresis.
4 5 PWR Power limit set An external resistor at this pin, in conjunction with the current sense resistor (R
S
),
sets the maximum power dissipation in the external series pass MOSFET.
5 6 VEE Negative supply Connect to the system negative supply voltage (typically -48V).
input
6 8 TIMER Timing capacitor An external capacitor at this pin sets the insertion time delay and the fault timeout
period. The capacitor also sets the restart timing of the LM5067-2.
7 9 SENSE Current sense The voltage across the current sense resistor (R
S
) is measured from VEE to this
input pin. If the voltage across R
S
reaches 50 mV the load current is limited and the
fault timer activates.
8 10 GATE Gate drive output Connect to the external N-channel MOSFET’s gate.
9 12 OUT Output feedback Connect to the external MOSFET’s drain. Internally used to determine the
MOSFET V
DS
voltage for power limiting, and to control the PGD output pin.
10 14 PGD Power Good An open drain output capable of sustaining 80V when off. When the external
indicator MOSFET V
DS
decreases below 1.23V the PGD pin switches high. When the
external MOSFET V
DS
increases above ≊2.5V the PGD pin switches low.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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