Datasheet

t
RESTART
= C
T
x
7 x 2.75V
2.5 PA
7 x 2.75V
85 PA
3.7V
2.5 PA
++
C
T
=
t
FAULT
x 85 PA
4V
= t
FAULT
x 2.13 x 10
-5
C
T
=
t1 x 6 PA
4V
= t1 x 1.5 x 10
-6
LM5067
www.ti.com SNVS532C –OCTOBER 2007–REVISED MARCH 2013
• The SOA (Safe Operating Area) chart of the device, and the thermal properties, should be used to determine
the maximum power dissipation threshold set by the R
PWR
resistor. The programmed maximum power
dissipation should have a reasonable margin from the maximum power defined by the FET's SOA chart if the
LM5067-2 is used since the FET will be repeatedly stressed during fault restart cycles. The FET manufacturer
should be consulted for guidelines.
• R
DS(on)
should be sufficiently low that the power dissipation at maximum load current (I
L(max)
2
x R
DS(on)
) does
not raise its junction temperature above the manufacturer’s recommendation.
If the device chosen for Q1 has a maximum V
GS
rating less than 13V, an external zener diode must be added
from its gate to source, with the zener voltage less than the maximum V
GS
rating. The zener diode’s forward
current rating must be at least 110 mA to conduct the GATE pull-down current during startup and in the circuit
breaker mode.
TIMER CAPACITOR, C
T
The TIMER pin capacitor (C
T
) sets the timing for the insertion time delay, fault timeout period, and restart timing
of the LM5067-2.
A) Insertion Delay - Upon applying the system voltage (V
SYS
) to the circuit, the external MOSFET (Q1) is held
off during the insertion time (t1 in Figure 6) to allow ringing and transients at V
SYS
to settle. Since each
backplane’s response to a circuit card plug-in is unique, the worst case settling time must be determined for each
application. The insertion time starts when the operating voltage (VCC-VEE) reaches the POR
IT
threshold, at
which time the internal 6 µA current source charges C
T
from 0V to 4.0V. The required capacitor value is
calculated from:
where
• t1 is the desired insertion delay (7)
For example, if the desired insertion delay is 250 ms, C
T
calculates to 0.38 µF. At the end of the insertion delay,
C
T
is quickly discharged by a 1.5 mA current sink.
B) Fault Timeout Period - During turn-on of the output voltage, or upon detection of a fault condition where the
current limit and/or power limit circuits regulate the current through Q1, C
T
is charged by the fault timer current
source (85 µA). The Fault Timeout Period is the time required for the TIMER pin voltage to reach 4.0V above
VEE, at which time Q1 is switched off. The required capacitor value for the desired Fault Timeout Period t
FAULT
is
calculated from:
(8)
For example, if the desired Fault Timeout Period is 16 ms, C
T
calculates to 0.34 µF. After a fault timeout, if the
LM5067-1 is in use, C
T
must be allowed to discharge to <0.3V by the 2.5 µA current sink, after which a power up
sequence can be initiated by external circuitry. See Fault Timer and Restart and Figure 8. If the LM5067-2 is in
use, after the Fault Timeout Period expires a restart sequence begins as described below (Restart Timing).
Since the LM5067 normally operates in power limit and/or current limit during a power up sequence, the Fault
Timeout Period MUST be longer than the time required for the output voltage to reach its final value. See TURN-
ON TIME.
C) Restart Timing If the LM5067-2 is in use, after the Fault Timeout Period described above, C
T
is discharged
by the 2.5 µA current sink to 1.25V. The TIMER pin then cycles through seven additional charge/discharge
cycles between 1.25V and 4.0V as shown in Figure 9. The restart time ends when the TIMER pin voltage
reaches 0.3V during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to:
= C
T
x 9.4 x 10
6
(9)
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM5067