Datasheet

t
ON
= -(R
L
x C
L
) x In
(I
LIM
x R
L
) - V
SYS
(I
LIM
x R
L
)
VCC
PGD
OUT
GND
GATESENSEVEE
VEE
LM5067
C
IN
R
IN
R
S
V
SYS
R
L
C
L
Q1
t
ON
=
V
SYS
x C
L
I
LIM
LM5067
www.ti.com SNVS532C –OCTOBER 2007–REVISED MARCH 2013
R
PWR
= 1.42 x 10
5
x R
S
x P
FET(LIM)
where
• P
FET(LIM)
is the desired power limit threshold for Q1
• R
S
is the current sense resistor described in the Current Limit section (3)
For example, if R
S
is 10 mΩ, and the desired power limit threshold is 60W, R
PWR
calculates to 85.2 kΩ. If Q1’s
power dissipation reaches the power limit threshold, Q1’s gate is modulated to control the load current, keeping
Q1’s power from exceeding the threshold. For proper operation of the power limiting feature, R
PWR
must be ≤150
kΩ. While the power limiting circuit is active, the fault timer is active as described in the Fault Timer & Restart
section. Typically, power limit is reached during startup, or when the V
DS
of Q1 increases due to a severe
overload or short circuit.
The programmed maximum power dissipation should have a reasonable margin relative to the maximum power
defined by the SOA chart if the LM5067-2 is used since the FET will be repeatedly stressed during fault restart
cycles. The FET manufacturer should be consulted for guidelines. The PWR pin can be left open if the
application does not require use of the power limit function.
TURN-ON TIME
The output turn-on time depends on whether the LM5067 operates in current limit only, or in both power limit and
current limit, during turn-on.
A) Turn-on with current limit only: If the current limit threshold is less than the current defined by the power
limit threshold at maximum V
DS
the circuit operates only at the current limit threshold during turn-on. Referring to
Figure 13a, as the drain current reaches I
LIM
, the gate-to-source voltage is controlled at V
GSL
to maintain the
current at I
LIM
. As the output voltage reaches its final value (V
DS
≊ 0V) the drain current reduces to the value
defined by the load, and the gate is charged to approximately 13V (V
GATE
). The time for the OUT pin voltage to
transition from zero volts to V
SYS
is equal to:
where
• C
L
is the load capacitance (4)
For example, if V
SYS
= -48V, C
L
= 1000 µF, and I
LIM
= 1A, t
ON
calculates to 48 ms. The maximum instantaneous
power dissipated in the MOSFET is 48W. This calculation assumes the time from t1 to t2 in Figure 13a is small
compared to t
ON
, and the load does not draw any current until after the output voltage has reached its final value,
and PGD switches high (Figure 11).
Figure 11. No Load Current During Turn-on
If the load draws current during the turn-on sequence (Figure 12), the turn-on time is longer than the above
calculation, and is approximately equal to:
where
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5067