Datasheet

I
LIMIT
Load
Current
GATE
Pin
TIMER
Pin
1 2 3 7 8
2.2 mA
pulldown
Fault Timeout
Period
0.3V
Fault
Detection
t
RESTART
1.25V
85
PA
4
V
52 PA
Gate Charge
All voltages are with respect to VEE
2.5 PA
LM5067
www.ti.com SNVS532C –OCTOBER 2007–REVISED MARCH 2013
Figure 9. Restart Sequence (LM5067-2)
Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (V
SYS
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. Typically
the UVLO level at V
SYS
is set with a resistor divider (R1-R3) as shown in Figure 4. When V
SYS
is less than the
UVLO level, the internal 22 µA current sink at UVLO/EN is enabled, the current source at OVLO is off, and Q1 is
held off by the 2.2 mA pull-down current at the GATE pin. V
SYS
reaches its UVLO level when the voltage at the
UVLO/EN pin reaches 2.5V above VEE. Upon reaching the UVLO level, the 22 µA current sink at the UVLO/EN
pin is switched off, increasing the voltage at the pin, providing hysteresis for this threshold. With the UVLO/EN
pin above 2.5V, Q1 is switched on by the 52 µA current source at the GATE pin.
See Application Information for a procedure to calculate the values of the threshold setting resistors (R1-R3). The
minimum possible UVLO level can be set by connecting the UVLO/EN pin to VCC. In this case Q1 is enabled
when the operating voltage (VCC – VEE) reaches the POR
EN
threshold (8.4V).
Over-Voltage Lock-Out (OVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (V
SYS
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. Typically
the OVLO level at V
SYS
is set with a resistor divider (R1-R3) as shown in Figure 4. If V
SYS
raises the OVLO pin
voltage more than 2.5V above VEE Q1 is switched off by the 2.2 mA pull-down current at the GATE pin, denying
power to the load. When the OVLO pin is above 2.5V, the internal 22 µA current source at OVLO is switched on,
raising the voltage at OVLO and providing threshold hysteresis. When the voltage at the OVLO pin is reduced
below 2.5V the 22 µA current source is switched off, and Q1 is enabled. See Application Information for a
procedure to calculate the threshold setting resistor values.
Shutdown/Enable Control
See Application Information for a description of how to use the UVLO/EN pin and/or the OVLO pin for remote
shutdown and enable control of the LM5067.
Power Good Pin
The Power Good output indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET. An
external pull-up resistor is required at PGD to an appropriate voltage to indicate the status to downstream
circuitry. The off-state voltage at the PGD pin must be more positive than VEE, and can be up to 80V above VEE
with transient capability to 100V. PGD is switched high at the end of the turn-on sequence when the voltage from
OUT to SENSE (the external MOSFET’s V
DS
) decreases below 1.23V. PGD switches low if the MOSFET’s V
DS
increases past 2.5V, if the system input voltage goes below the UVLO threshold or above the OVLO threshold,
or if a fault is detected. The PGD output is high when the operating voltage (VCC-VEE) is less than 2V.
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