Datasheet

Restart
Control
VCC
OVLO
VEE
System Gnd
VEE
SENSE
V
SYS
C
IN
R
IN
R1
R2
R
S
UVLO/EN
LM5067-1
R3
LM5067
SNVS532C –OCTOBER 2007–REVISED MARCH 2013 www.ti.com
Circuit Breaker
If the load current increases rapidly (e.g., the load is short-circuited) the current in the sense resistor (R
S
) may
exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds
approximately twice the current limit threshold (100 mV/R
S
), Q1’s gate is quickly pulled down by the 110 mA pull-
down current at the GATE pin, and a Fault Timeout Period begins. When the voltage across R
S
falls below 100
mV the 110 mA pull-down current at the GATE pin is switched off, and the gate voltage of Q1 is then determined
by the current limit or the power limit functions. If the TIMER pin reaches 4.0V before the current limiting or
power limiting condition ceases, Q1 is switched off by the 2.2 mA pull-down current at the GATE pin as
described in the Fault Timer & Restart section.
Power Limit
An important feature of the LM5067 is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5067 determines
the power dissipation in Q1 by monitoring its drain-source voltage (OUT to SENSE), and the drain current
through the sense resistor (SENSE to VEE). The product of the current and voltage is compared to the power
limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold,
the GATE voltage is modulated to reduce the current in Q1, and the fault timer is active as described in the Fault
Timer & Restart section.
Fault Timer and Restart
When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either
limiting function is active, an 85 µA fault timer current source charges the external capacitor (C
T
) at the TIMER
pin as shown in Figure 9 (Fault Timeout Period). If the fault condition subsides before the TIMER pin reaches
4.0V, the LM5067 returns to the normal operating mode and C
T
is discharged by the 2.5 µA current sink. If the
TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is switched off by a 2.2 mA pull-down current at
the GATE pin. The subsequent restart procedure depends on which version of the LM5067 is in use.
The LM5067-1 latches the GATE pin low at the end of the Fault Timeout Period, and C
T
is discharged by the 2.5
µA fault current sink. The GATE pin is held low until a power up sequence is externally initiated by cycling the
input voltage (V
SYS
), or momentarily pulling the UVLO/EN pin within 2.5V of VEE with an open-collector or open-
drain device as shown in Figure 8. The voltage across C
T
must be <0.3V for the restart procedure to be effective.
Figure 8. Latched Fault Restart Control
The LM5067-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 4.0V
and 1.25V seven times after the Fault Timeout Period, as shown in Figure 9. The period of each cycle is
determined by the 85 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor C
T
.
When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 52 µA current source at the GATE pin
turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart cycle repeat.
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