Datasheet

TIMER Pin
Load
Current
PGD
UVLO
Limiting
Normal Operation
GATE Pin
Insertion Time
Operating
Voltage
Output
Voltage
VEE
All waveforms and voltages are with respect to VEE
except System Input Voltage and Output Voltage.
2.5 PA
85PA
52 PA source
4V
0V
2.2 mA pull-down
6 PA
1.25V
I
LIMIT
V
SYS
pull-down
110 mA
0V
V
SYS
V
Z
POR
IT
System
Input
Voltage
(VCC
±
VEE)
LM5067
(OUT Pin)
t3
t2
In-rush
t1
LM5067
SNVS532C –OCTOBER 2007–REVISED MARCH 2013 www.ti.com
The GATE pin switches on Q1 when V
SYS
exceeds the UVLO threshold (UVLO pin >2.5V above VEE). If V
SYS
exceeds the UVLO threshold at the end of the insertion time, Q1 is switched on at that time. The GATE pin
sources 52 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by the
LM5067’s operating voltage (V
Z
) to approximately 13V. During power up, as the voltage at the OUT pin increases
in magnitude with respect to Ground, the LM5067 monitors Q1’s drain current and power dissipation. In-rush
current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush
limiting interval (t2 in Figure 6) an internal current source charges C
T
at the TIMER pin. When the load current
reduces from the limiting value to a value determined by the load the in-rush limiting interval is complete and C
T
is discharged. The PGD pin switches high when the voltage at the OUT pin reaches to within 1.25V of the
voltage at the SENSE pin.
If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault
is declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.
Figure 6. Power Up Sequence (Current Limit only)
Operating Voltage
The LM5067 operating voltage is the voltage from VCC to VEE. The maximum operating voltage is set by an
internal 13V zener diode. With the IC connected as shown in Figure 4, the LM5067 controller operates in the
voltage range between VEE and VEE+13V. The remainder of the system voltage is dropped across the input
resistor R
IN
, which must be selected to pass at least 2 mA into the LM5067 at the minimum system voltage.
12 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM5067