Datasheet

Load
VCC
GND
BACKPLANE
PGD
OUT
LIVE
Q1
R
S
GATESENSEVEE
V
SYS
R
IN
LM5067
-48V
PLUG
-
IN BOARD
C
L
C
IN
LM5067
www.ti.com SNVS532C –OCTOBER 2007–REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
The LM5067 is designed to control the in-rush current to the load upon insertion of a circuit card into a live
backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage, and
the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing
possible unintended resets. During the system power up, the maximum power dissipation in the series pass
device is limited to a safe value within the device’s Safe Operating Area (SOA). After the system power up is
complete, the LM5067 monitors the load for excessive currents due to a fault or short circuit at the load. Limiting
the load current and/or the power in the external MOSFET for an extended period of time results in the shutdown
of the series pass MOSFET. After a fault event, the LM5067-1 latches off until the circuit is re-enabled by
external control, while the LM5067-2 automatically restarts with defined timing. The circuit breaker function
quickly switches off the series pass device upon detection of a severe over-current condition caused by, e.g. a
short circuit at the load. The Power Good (PGD) output pin indicates when the output voltage is close to the
normal operating value. Programmable under-voltage lock-out (UVLO) and over-voltage lock-out (OVLO) circuits
shut down the LM5067 when the system input voltage is outside the desired operating range. The typical
configuration of a circuit card with LM5067 hot swap protection is shown in Figure 5.
Figure 5. LM5067 Application
The LM5067 can be used in a variety of applications, other than plug-in boards, to monitor for excessive load
current, provide transient protection, and ensuring the voltage to the load is within preferred limits. The circuit
breaker function protects the system from a sudden short circuit at the load. Use of the UVLO/EN pin allows the
LM5067 to be used as a solid state relay. The PGD output provides a status indication of the voltage at the load
relative to the input system voltage.
Power Up Sequence
The system voltage range of the LM5067 is -9V to -80V, with a transient capability to -100V. Referring to the
Block Diagram, Figure 4, and Figure 6, as the system voltage (V
SYS
) initially increases from zero, the external N-
channel MOSFET (Q1) is held off by an internal 110 mA pull-down current at the GATE pin. The strong pull-
down current at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller)
capacitance is charged. When the operating voltage of the LM5067 (VCC – VEE) reaches the POR
IT
threshold
(7.7V) the insertion timer starts. During the insertion time, the capacitor at the TIMER pin (C
T
) is charged by a 6
µA current source, and Q1 is held off by a 2.2 mA pull-down current at the GATE pin regardless of the system
voltage. The insertion time delay allows ringing and transients at V
SYS
to settle before Q1 can be enabled. The
insertion time ends when the TIMER pin voltage reaches 4.0V above VEE, and C
T
is then quickly discharged by
an internal 1.5 mA pull-down current. After the insertion time, the LM5067 control circuitry is enabled when the
operating voltage reaches the POR
EN
threshold (8.4V). As V
SYS
continues to increase, the LM5067 operating
voltage is limited at ≊13V by an internal zener diode. The remainder of the system voltage is dropped across the
input resistor R
IN
.
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