Datasheet

GND
LOAD
VCC
VEE SENSETIMER GATE
OVLO
PGD
LM5067
PWR
OUT
R
PG
R
IN
C
IN
Q1
R
S
R
PWR
C
T
R1
R2
R3
V
SYS
(- 48V)
UVLO /EN
GATE
Fault
Timer
1.25V
TIMER
1.23V/
2.5V
Current Limit
Threshold
8.4/8.3V
Enable POR
TIMER AND GATE
LOGIC CONTROL
Power Limit
Threshold
Gate
Control
1.55 mA
End
Insertion
Time
0.3V
7.7V
Vcc
Insertion Timer POR
110
mA
VEE
SENSE
OUT
PWR
OVLO
UVLO/EN
Insertion
Timer
Fault
Discharge
PGD
Vcc
50 mV
2.2 mA
4.0V
2.5V
2.5V
23 PA
22 PA
22 PA
2.5 PA
85 PA
6 PA
52 PA
V
DS
1 M:
13V
Vcc
V
Z
Vee
VCC
Vee
Vee
Vee
Vee
Vee
Current Limit
Power Limit
Control
Vcc
LM5067
All voltages are with respect to VEE
I
D
LM5067
SNVS532C –OCTOBER 2007–REVISED MARCH 2013 www.ti.com
BLOCK DIAGRAM
Figure 4. Basic Application Circuit
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