Datasheet

LM5066
Inductive
Load
VIN
GND
+48V
GND
LIVE
POWER
SOURCE
PLUG-IN BOARD
OUT
Q1
SENSE
VIN_K
AGND
V
OUT
R
S
V
IN
C
L
Z
1
D
1
LM5066
www.ti.com SNVS655G –JUNE 2011–REVISED FEBRUARY 2013
SYSTEM CONSIDERATIONS
A) Continued proper operation of the LM5066 hot swap circuit requires a voltage clamping element present on
the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in
Figure 16. The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts
off the load current. If the TVS is not present, inductance in the supply lines will generate a voltage transient at
shut-off which can exceed the absolute maximum rating of the LM5066, resulting in its destruction. For low
current solutions (<2A), a capacitor may be sufficient to limit the voltage surge, however this comes at the
expense of input surge current on card insertion.
If the load powered by the LM5066 hot swap circuit has inductive characteristics, a Schottky diode is required
across the LM5066’s output, along with some load capacitance. The capacitance and the diode are necessary to
limit the negative excursion at the OUT pin when the load current is shut off. If the OUT pin transitions more than
0.3V negative the LM5066 can be permanently damaged. See Figure 16.
Figure 16. Output Diode Required for Inductive Loads
PC BOARD GUIDELINES
The following guidelines should be followed when designing the PC board for the LM5066:
- Place the LM5066 close to the board’s input connector to minimize trace inductance from the connector to the
MOSFET.
- Place a TVS, Z
1
, directly adjacent to the VIN and GND pins of the LM5066 to help minimize voltage transients
which may occur on the input supply line. The TVS should be chosen such that the peak V
IN
is just lower the
TVS reverse-bias voltage. Transients of 20 volts or greater over the nominal input voltage can easily occur when
the load current is shut off. A small capacitor may be sufficient for low current sense applications (I < 2A). It is
recommended to test the VIN input voltage transient performance of the circuit by current limiting or shorting the
load and measuring the peak input voltage transient.
- Place a 1 µF ceramic capacitor as close as possible to VREF pin.
- Place a 1 µF ceramic capacitor as close as possible to VDD pin.
- Minimize the inductance between the VIN and VIN_K pins. There are anti-parallel diodes between these pins so
any voltage greater than 0.3V in either polarity will cause significant current flow through the diodes, which can
result in device failure. Do not place any resistors between these two nodes.
- Minimize the impedance between the VIN_K and SENSE pins. There are anti-parallel diodes between these
pins so any voltage greater than 0.3V in either polarity will cause significant current flow through the diodes,
which can result in device failure.
- The sense resistor (R
S
) should be placed close to the LM5066. A trace should connect the VIN pad and Q
1
pad
of the sense resistor to VIN_K and SENSE pins, respectively. Connect R
S
using the Kelvin techniques shown in
Figure 7.
- The high current path from the board’s input to the load (via Q
1
), and the return path, should be parallel and
close to each other to minimize loop inductance.
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