Datasheet

VIN
UVLO/EN
OVLO
GND
10k
R3
R4
2.48V
2.46V
TIMER AND
GATE
LOGIC CONTROL
LM5066
V
IN
21 PA
20 PA
LM5066
www.ti.com SNVS655G –JUNE 2011–REVISED FEBRUARY 2013
(28)
(29)
V
UV(HYS)
= R1 x 20 µA (30)
(31)
(32)
Option C: The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 12.
Q1 is switched on when the VIN voltage reaches the POR
EN
threshold (≊8.6V). The OVLO thresholds are set
using R3, R4. Their values are calculated using the procedure in Option B.
Figure 12. UVLO = POR
EN
Option D: The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as
described in Option B or Option C.
POWER GOOD PIN
When the voltage at the FB pin increases above its threshold the internal pulldown acting on the PGD pin is
disabled allowing PGD to rise to V
PGD
through the pull-up resistor, R
PG
, as shown in Figure 14. The pull-up
voltage (V
PGD
) can be as high as 80V, and can be higher or lower than the voltages at VIN and OUT. VDD is a
convenient choice for V
PGD
as it allows interface to low voltage logic and avoids glitching on PGD during power-
up. If a delay is required at PGD, suggested circuits are shown in Figure 15. In Figure 15A, capacitor C
PG
adds
delay to the rising edge, but not to the falling edge. In Figure 15B, the rising edge is delayed by R
PG1
+ R
PG2
and
C
PG
, while the falling edge is delayed a lesser amount by R
PG2
and C
PG
. Adding a diode across R
PG2
(Figure 15C) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the
falling edge.
Setting the output threshold for the PGD pin requires two resistors (R4, R5) as shown in Figure 13. While
monitoring the output voltage is shown in Figure 13, R4 can be connected to any other voltage which requires
monitoring.
The resistor values are calculated as follows:
Choose the upper and lower threshold (V
PGDH
) and (V
PGDL
) at V
OUT
.
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(34)
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