Datasheet
VIN
UVLO/EN
OVLO
GND
R1
R2
R3
2.48V
2.46V
TIMER AND
GATE
LOGIC CONTROL
LM5066
V
IN
21 PA
20 PA
LM5066
www.ti.com
SNVS655G –JUNE 2011–REVISED FEBRUARY 2013
For example, if C
T
= 0.8 µF, t
RESTART
= 7.9 seconds. At the end of the restart time, Q
1
is switched on. If the fault
is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately
0.5% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the LM5066 enables the series pass device (Q
1
) when the
input supply voltage (V
IN
) is within the desired operational range. If V
IN
is below the UVLO threshold, or above
the OVLO threshold, Q
1
is switched off, denying power to the load. Hysteresis is provided for each threshold.
Option A: The configuration shown in Figure 10 requires three resistors (R1-R3) to set the thresholds.
Figure 10. UVLO and OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
- Choose the upper UVLO threshold (V
UVH
), and the lower UVLO threshold (V
UVL
).
- Choose the upper OVLO threshold (V
OVH
).
- The lower OVLO threshold (V
OVL
) cannot be chosen in advance in this case, but is determined after the values
for R1-R3 are determined. If V
OVL
must be accurately defined in addition to the other three thresholds, see
Option B below. The resistors are calculated as follows:
(11)
(12)
(13)
The lower OVLO threshold is calculated from:
(14)
As an example, assume the application requires the following thresholds: V
UVH
= 36V, V
UVL
= 32V, V
OVH
= 60V.
(15)
(16)
(17)
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LM5066