Datasheet

0
0
Drain Current
0
t1
0
0
t2
t3
a) Current Limit Only
V
DS
t
ON
b) Power Limit and Current Limit
V
DS
Drain Current
t
ON
0
V
IN
I
LIM
V
GATE
V
GSL
V
TH
V
IN
I
LIM
V
GATE
V
GSL
V
TH
I
P
Gate-to-Source Voltage
LM5066
SNVS655G –JUNE 2011–REVISED FEBRUARY 2013 www.ti.com
Figure 9. MOSFET Power Up Waveforms
TIMER CAPACITOR, C
T
The TIMER pin capacitor (C
T
) sets the timing for the insertion time delay, fault timeout period, and the restart
timing of the LM5066.
A) Insertion Delay -Upon applying the system voltage (V
IN
) to the circuit, the external MOSFET (Q
1
) is held off
during the insertion time (t
1
in Figure 2) to allow ringing and transients at V
IN
to settle. Since each backplane’s
response to a circuit card plug-in is unique, the worst case settling time must be determined for each application.
The insertion time starts when VIN reaches the POR threshold, at which time the internal 4.8 µA current source
charges C
T
from 0V to 3.9V. The required capacitor value is calculated from:
(7)
For example, if the desired insertion delay is 250 ms, C
T
calculates to 0.3 µF. At the end of the insertion delay,
C
T
is quickly discharged by a 1.5 mA current sink.
B) Fault Timeout Period -During in-rush current limiting or upon detection of a fault condition where the current
limit and/or power limit circuits regulate the current through Q
1
, the fault timer current source (75 µA) is switched
on to charge C
T
. The Fault Timeout Period is the time required for the TIMER pin voltage to reach 3.9V, at which
time Q
1
is switched off. The required capacitor value for the desired Fault Timeout Period t
FAULT
is calculated
from:
(8)
For example, if the desired Fault Timeout Period is 15 ms, C
T
calculates to 0.3 µF. C
T
is discharged by the 2.5
µA current sink at the end of the Fault Timeout Period. After the Fault Timeout Period, if retry is disabled, the
LM5066 latches the GATE pin low until a power up sequence is initiated by external circuitry. When the Fault
Timeout Period of the LM5066 expires, a restart sequence starts as described below (Restart Timing). During
consecutive cycles of the restart sequence, the fault timeout period is shorter than the initial fault time out period
described above by approximately 8% since the voltage at the TIMER pin starts ramping up from 0.3V rather
than ground.
Since the LM5066 normally operates in power limit and/or current limit during a power up sequence, the Fault
Timeout Period MUST be longer than the time required for the output voltage to reach its final value. See the
TURN-ON TIME section.
C) Restart Timing For the LM5066, after the Fault Timeout Period described above, C
T
is discharged by the 2.5
µA current sink to 1.1V. The TIMER pin then cycles through seven additional charge/discharge cycles between
1.1V and 3.9V as shown in Figure 4. The restart time ends when the TIMER pin voltage reaches 0.3V during the
final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to:
(9)
= C
T
x 9.5 x 10
6
(10)
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