Datasheet

OUT
UVLO/EN
VIN
GATE
DIODE
R
1
FB
OVLO
SDAI
SCL
PGD
SENSE
VDD
SMBA
CL
RETRY
VAUX
VDD
VREF TIMER
PWR
AGND
LM5066
Auxillary ADC Input
(0V ± 2.97V)
V
OUT
C
OUT
R
PG
V
IN
1 PF
1 PF
R
PWR
ADR2
ADR1
ADR0
N/C
N/C
VIN_K
GND
SDAO
R
S
R
2
R
3
C
TIMER
R
4
R
5
MMBT3904
Z
1
D
1
3 mÖ
5.0SMDJ60A
B380-13-F
150 kÖ
IPB027N10N3 G
10 kÖ
100 kÖ
191 kÖ
7.5 kÖ
8.66 kÖ
N/C
16.2 kÖ
0.15 PF
PMBus Address = 40h
Continuous Retry
50 mV Current Limit
Q
2
Q
1
LM5066
SNVS655G –JUNE 2011–REVISED FEBRUARY 2013 www.ti.com
APPLICATION INFORMATION
Figure 6. Typical Application Circuit
DESIGN-IN PROCEDURE
Refer to Figure 6 for Typical Application Circuit. The following is the step-by-step procedure for hardware design
of the LM5066. This procedure refers to section numbers that provide detailed information on the following
design steps. The recommended design-in procedure is as follows:
MOSFET Selection: Determine MOSFET based on breakdown voltage, current and power ratings.
Current Limit, R
S
: Determine the current limit threshold (I
LIM
). This threshold must be higher than the normal
maximum load current, allowing for tolerances in the current sense resistor value and the LM5066 Current Limit
threshold voltage. Use Equation 1 to determine the value for R
S
.
Power Limit Threshold: Determine the maximum allowable power dissipation for the series pass MOSFET (Q
1
),
using the device’s SOA information. Use Equation 2 to determine the value for R
PWR
. Note that many MOSFET
manufacturers do not accurately specify the device SOA so it is usually beneficial to choose a conservative value
when selecting R
PWR
.
Turn-on Time and TIMER Capacitor, C
T
: Determine the value for the timing capacitor at the TIMER pin (C
T
)
using Equation 7 and Equation 8. The fault timeout period (t
FAULT
) MUST be longer than the circuit’s turn-on time.
The turn-on time can be estimated using the equations in the TURN-ON TIME section, but should be verified
experimentally. Review the resulting insertion time and the restart timing if retry is enabled.
UVLO, OVLO: Choose option A, B, C, or D from the UVLO, OVLO section to set the UVLO and OVLO
thresholds and hysteresis. Use the procedure for the appropriate option to determine the resistor values at the
UVLO/EN and OVLO pins.
Power Good: Choose the appropriate output voltage and calculate the required resistor divider from the output
voltage to the FB pin. Choose either VDD or OUT to connect a properly sized pull-up resistor for the Power Good
output (PGD).
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