Datasheet

10
9
8
11
12
1
2
3
4
5
7
6
FB
RETRY
NC
PWR
GATE
SENSE
VIN_K
NC
VIN
CL
PGD
OUT
UVLO/EN
TIMER
25
26
27
28
21
22
23
24
13
14
19
20
OVLO
AGND
SDAI
GND
SDAO
ADR2
ADR1
VDD
VAUX
ADR0
SMBA
SCL
18
17
16
15
VREF
DIODE
OUT
UVLO/EN
VIN
GATE
DIODE
R
1
FB
OVLO
SDAI
SCL
PGD
SENSE
VDD
SMBus
Interface
SMBA
CL
RETRY
VAUX
VDD
VREF
TIMER
PWR
AGND
LM5066
Auxillary ADC Input
(0V ± 2.97V)
V
OUT
C
OUT
R
PG
V
IN
1 PF
1 PF
R
PWR
ADR2
ADR1
ADR0
VDD
N/C
N/C
VIN_K
GND
SDAO
R
S
R
2
R
3
C
TIMER
R
4
R
5
C
IN
Z
1
D
1
Q
2
Q
1
LM5066
SNVS655G –JUNE 2011–REVISED FEBRUARY 2013 www.ti.com
Typical Application Schematic
Connection Diagram
Solder exposed pad to ground.
Top View
28-Lead HTSSOP with
Exposed Pad
PIN DESCRIPTIONS
Pin
Name Description Applications Information
No.
Pad Exposed Pad Exposed pad of HTSSOP Solder to the ground plane to reduce thermal resistance
package
1 OUT Output feedback Connect to the output rail (external MOSFET source). Internally used to determine
the MOSFET V
DS
voltage for power limiting, and to monitor the output voltage.
2 GATE Gate drive output Connect to the external MOSFET's gate.
2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
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