Datasheet

LM5066
www.ti.com SNVS655G –JUNE 2011–REVISED FEBRUARY 2013
The SMBus address of the LM5066 is captured based on the states of the ADR0, ADR1, and ADR2 pins (GND,
NC, VDD) during turn on and is latched into a volatile register once VDD has exceeded its POR threshold of
4.1V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground.
Pulling the VREF pin low will also reset the logic and erase the volatile memory of the LM5066. Once released,
the VREF pin will charge up to its final value and the address will be latched into a volatile register once the
voltage at the VREF exceeds 2.55V.
Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM5066