Datasheet

Shutdown
Control
LM5066
VIN
V
IN
UVLO/EN
OVLO
GND
R1
R2
R3
LM5066
www.ti.com SNVS655G –JUNE 2011–REVISED FEBRUARY 2013
Under-Voltage Lockout (UVLO)
The series pass MOSFET (Q
1
) is enabled when the input supply voltage (V
IN
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) levels. Typically
the UVLO level at V
IN
is set with a resistor divider (R1-R3) as shown in Figure 5. Refering to the Block Diagram
when V
IN
is below the UVLO level, the internal 20 µA current source at UVLO is enabled, the current source at
OVLO is off, and Q
1
is held off by the 4.2 mA pull-down current at the GATE pin. As V
IN
is increased, raising the
voltage at UVLO above its threshold the 20 µA current source at UVLO is switched off, increasing the voltage at
UVLO, providing hysteresis for this threshold. With the UVLO/EN pin above its threshold, Q
1
is switched on by
the 20 µA current source at the GATE pin if the insertion time delay has expired.
See the Application Information section for a procedure to calculate the values of the threshold setting resistors
(R1-R3). The minimum possible UVLO level at V
IN
can be set by connecting the UVLO/EN pin to VIN. In this
case Q
1
is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power up
an UVLO condition will cause the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the
STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h)
registers to be toggled high and SMBA pin will be pulled low unless this feature is disabled using the
ALERT_MASK (D8h) register.
Over-Voltage Lockout (OVLO)
The series pass MOSFET (Q
1
) is enabled when the input supply voltage (V
IN
) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) levels. If V
IN
raises
the OVLO pin voltage above its threshold, Q
1
is switched off by the 4.2 mA pull-down current at the GATE pin,
denying power to the load. When the OVLO pin is above its threshold, the internal 21 µA current source at OVLO
is switched on, raising the voltage at OVLO to provide threshold hysteresis. When V
IN
is reduced below the
OVLO level Q
1
is re-enabled. An OVLO condition will toggle the VIN_OV_FAULT bit in the STATUS_INPUT
(7Ch) register, the INPUT bit in the STATUS_WORD (79h) register and the VIN_OVERVOLTAGE_FAULT bit in
the DIAGNOSTIC_WORD (E1h) register. The SMBA pin will be pulled low unless this feature is disabled using
the ALERT_MASK (D8h) register.
See the Application Information section for a procedure to calculate the threshold setting resistor values.
Shutdown Control
The load current can be remotely switched off by taking the UVLO/EN pin below its threshold with an open
collector or open drain device, as shown in Figure 5. Upon releasing the UVLO/EN pin the LM5066 switches on
the load current with in-rush current and power limiting.
Figure 5. Shutdown Control
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80V in the off-state, and transients up to 100V. An external pull-up resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Block Diagram, when the
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