Datasheet

1.1V
1 2 3 7 8
4.2 mA pulldown
Fault
Detection
GATE
Pin
Load
Current
T
I
LIMI
t
RESTART
Fault Timeout
Period
20 PA
Gate Charge
2.5
PA
3.9V
75 PA
0.3V
TIMER
Pin
LM5066
Restart
Control
VIN
V
IN
UVLO/EN
OVLO
GND
R1
R2
R3
LM5066
SNVS655G –JUNE 2011–REVISED FEBRUARY 2013 www.ti.com
Fault Timer & Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q
1
is modulated to regulate the load current and power dissipation in Q
1
. When either
limiting function is active, a 75 µA fault timer current source charges the external capacitor (C
T
) at the TIMER pin
as shown in Figure 2 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout Period
before the TIMER pin reaches 3.9V, the LM5066 returns to the normal operating mode and C
T
is discharged by
the 1.5 mA current sink. If the TIMER pin reaches 3.9V during the Fault Timeout Period, Q
1
is switched off by a
4.2 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM5066 latches the GATE pin low at the end of the Fault Timeout Period. C
T
is
then discharged to ground by the 2.5 µA fault current sink. The GATE pin is held low by the 4.2 mA pull-down
current until a power up sequence is externally initiated by cycling the input voltage (V
IN
), or momentarily pulling
the UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 3. The
voltage at the TIMER pin must be <0.3V for the restart procedure to be effective. The TIMER_LATCHED_OFF
bit in the DIAGNOSTIC_WORD (E1h) register will remain high while the latched off condition persists.
Figure 3. Latched Fault Restart Control
The LM5066 provides an automatic restart sequence which consists of the TIMER pin cycling between 3.9V and
1.1V seven times after the Fault Timeout Period, as shown in Figure 4. The period of each cycle is determined
by the 75 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor C
T
. When the
TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 20 µA current source at the GATE pin turns on
Q
1
. If the fault condition is still present, the Fault Timeout Period and the restart sequence repeat. The RETRY
pin allows selecting no retries or infinite retries. Finer control of the retry behavior can be achieved through the
DEVICE_SETUP (D9h) register. Retry counts of 0, 1, 2, 4, 8, 16 or infinite may be selected by setting the
appropriate bits in the DEVICE_SETUP (D9h) register.
Figure 4. Restart Sequence
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