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LM5066

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SNVS655G –JUNE 2011–REVISED FEBRUARY 2013

During the insertion time (t

in Figure 2) the GATE pin is held low by a 4.2 mA pull-down current. This maintains

in the off-state until the end of t

, regardless of the voltage at VIN or UVLO. Following the insertion time,

during t

in Figure 2 the gate voltage of Q

is modulated to keep the current or power dissipation level from

exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is

charging. If the current and power limiting cease before the TIMER pin reaches 3.9V the TIMER pin capacitor

then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the

TIMER pin reached 3.9V during t

, the GATE pin is then pulled low by the 4.2 mA pull-down current. The GATE

pin is then held low until either a power up sequence is initiated (RETRY pin to VDD), or an automatic retry is

attempted (RETRY pin to GROUND or floating). See the Fault Timer & Restart section. If the system input

voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the

4.2 mA pull-down current to switch off Q

Current Limit

The current limit threshold is reached when the voltage across the sense resistor R

(VIN to SENSE) exceeds

the internal voltage limit of 26 mV or 50 mV depending on whether the CL pin is connected to VDD or GND,

respectively. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q

While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If

the load current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5066

resumes normal operation. If the current limit condition persists for longer than the Fault Timeout Period set by

, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD (79h)

SMBA pin will be asserted. SMBA toggling can be disabled using the ALERT_MASK (D8h) register. For proper

operation, the R

resistor value should be no higher than 200 mΩ. Higher values may create instability in the

current limit control loop. The current limit threshold pin value may be overridden by setting appropriate bits in

the DEVICE_SETUP register (D9h).

Circuit Breaker

If the load current increases rapidly (for example, the load is short circuited) the current in the sense resistor (R

)

may exceed the current limit threshold before the current limit control loop is able to respond. If the current

exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q

is quickly switched off by the 115 mA pull-

down current at the GATE pin, and a Fault Timeout Period begins. When the voltage across R

falls below the

circuit breaker (CB) threshold, the 115 mA pull-down current at the GATE pin is switched off, and the gate

voltage of Q

is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9V

before the current limiting or power limiting condition ceases, Q

is switched off by the 4.2 mA pull-down current

at the GATE pin as described in the Fault Timer & Restart section. A circuit breaker event will cause the

CIRCUIT BREAKER FAULT bit in the STATUS_MFR_SPECIFIC (80h) and DIAGNOSTIC_WORD (E1h)

registers to be toggled high and SMBA pin will be asserted unless this feature is disabled using the

ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by setting appropriate bits

in the DEVICE_SETUP (D9h) register.

Power Limit

An important feature of the LM5066 is the MOSFET power limiting. The Power Limit function can be used to

maintain the maximum power dissipation of MOSFET Q

within the device SOA rating. The LM5066 determines

the power dissipation in Q

by monitoring its drain-source voltage (SENSE to OUT), and the drain current

through the R

(VIN to SENSE). The product of the current and voltage is compared to the power limit threshold

programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE

voltage is modulated to regulate the current in Q

. While the power limiting circuit is active, the fault timer is

active as described in the Fault Timer & Restart section. If the power limit condition persists for longer than the

Fault Timeout Period set by the timer capacitor, C

, the IIN OC Fault bit in the STATUS_INPUT (7Ch) register,

the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the

DIAGNOSTIC_WORD (E1h) register will be toggled high and SMBA pin will be asserted unless this feature is

disabled using the ALERT_MASK (D8h) register.

Product Folder Links: LM5066