Datasheet

Normal Operation
Insertion Time
POR
Load
Current
In rush
Limiting
FB
4.8 PA
75 PA
3.9V
2.5 PA
20 PA source
GATE
TIMER
UVLO
V
IN
VIN
4.2 mA pull-down
115 mA
pull-down
I
LIMIT
2.46V
t
2
t
1
t
3
PGD
LM5066
SNVS655G –JUNE 2011–REVISED FEBRUARY 2013 www.ti.com
and transients at V
IN
to settle before Q
1
is enabled. The insertion time ends when the TIMER pin voltage reaches
3.9V. C
T
is then quickly discharged by an internal 1.5 mA pull-down current. The GATE pin then switches on Q
1
when V
IN
exceeds the UVLO threshold. If V
IN
is above the UVLO threshold at the end of the insertion time, Q
1
the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q
1
. The maximum voltage from the
gate to source of the Q
1
is limited by an internal 16.5V zener diode.
As the voltage at the OUT pin increases, the LM5066 monitors the drain current and power dissipation of
MOSFET Q
1
. In-rush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the in-rush limiting interval (t
2
in Figure 2) an internal 75 µA fault timer current source charges C
T
. If
Q
1
’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 3.9V, the 75 µA current source is switched off, and C
T
is discharged by the internal 2.5 µA current
sink (t
3
in Figure 2). The in-rush limiting will no longer engage unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9V before in-rush current limiting or power limiting ceases during t
2
, a fault is
declared and Q
1
is turned off. See the Fault Timer & Restart section for a complete description of the fault mode.
The LM5066 will assert the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the
volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device
operation and will remain high until a CLEAR_FAULTS command is received.
Figure 2. Power Up Sequence (Current Limit Only)
Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate (Q
1
). During
normal operating conditions (t
3
in Figure 2) the gate of Q
1
is held charged by an internal 20 µA current source.
The charge pump peak voltage is roughly 13.5V, which will force a V
GS
across Q1 of 13.5V under normal
operation. When the system voltage is initially applied, the GATE pin is held low by a 115 mA pull-down current.
This helps prevent an inadvertent turn-on of Q
1
through its drain-gate capacitance as the applied system voltage
increases.
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