Datasheet

UVLO/EN
VIN
OVLO
SDAI
PGD
SENSE
SMBA
VREF
AGND
LM5066
V
OUT
V
IN
VIN_K
GND
SDAO
R
S
3 m
Z
1
5.0SMDJ60A
D
1
B380-13-F
VREF
VAUX
R
5
0
R
6
10 k
C
7
1000 pF
C
6
1 F
Q
2
CMPT3904
ADR2
ADR2
ADR2
CL
FB
VDD
VDD
C
5
1 F
TIMER
C
4
0.15 F
PWR
VDD
R
17
16.2 k
R
7
10 k
TIMER
FB
PGD
R
20
154 k
RETRY
R
9
100 k
DIODE
VAUX
OUT
GATE
R
8
4.99
C
9
220 F
UVLO/EN
OVLO
C
1
OPEN
R
2
16.9 k
R
3
191 k
R
21
OPEN
R
4
8.25 k
R
1
200 k
SCL
VDD
V
IN_S
V
IN_GND
V
OUT_S
V
OUT_GND
R
15
10 k
R
14
10 k
R
13
10 k
SDA
SCL
SMBA
DUTGND
J6
J3
R
18
R
10
R
11
R
12
R
16
SCL
SDA
CTRL1
SMBA
CTRL2
PGD
PGD
R
18,10,11,12,16
100
SCL
SDA
CTRL1
SMBA
CTRL2
1
1
SENSE
GATE
VIN_K
V
OUT_S
GND
SWITCHES
CONNECTORS
ADR2
ADR1
ADR0
CL
RETRY
VDD
HIGH-Z
GND
Q
1
IPB027N10N3
Schematic www.ti.com
3 Schematic
Figure 1. Evaluation Board Schematic
The schematic for the LM5066 evaluation board is shown in Figure 1. Connections to the PMBus
TM
interface are provided by J6. Banana connectors provide input and output connections. Pins ADR0, ADR1,
and ADR2 are connected to switches that set the PMBus
TM
address of the device to one of 27 unique
addresses. Pins RETRY and CL are also connected to switches, allowing for hardware programmability of
the retry and current limit parameters, respectively. Test points are provided to connect to the input
voltage, output voltage, VAUX, PGD, VREF, VDD, SENSE, GATE, FB, UVLO/EN, OVLO, SCL, SDA,
SMBA and the TIMER pins.
2
AN-2160 LM5066 Evaluation Board SNVA487A–August 2011–Revised April 2013
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