Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

OUT

GND

PGD

GATE

OUT

R20

LM5066

2.46V

20 PA

POWER

GOOD

VDD

PGD and FB Pins

www.ti.com

14 PGD and FB Pins

During turn-on, the Power Good pin (PGD) will not be able to pull low until the voltage at VIN increases

above ≊1.6V. Pulling the PGD pin up to VDD will keep the PGD pin low during this region because VDD

does not turn on until VIN increases above ≊7V. When the voltage at the board’s output pin increases

above 40V (typ), PGD switches high. PGD switches low when the output voltage decreases below 37V

(typ). Additionally, PGD switches low if the UVLO/EN pin is taken below its threshold regardless of the

output voltage.

The output voltage threshold for the PGD pin is set with two resistors (RFB1, RFB2 on the GUI, R

and

on the board) at the FB pin.

Figure 13. Programming the PGD Threshold

A pull-up voltage and pull-up resistor are required at PGD as shown in Figure 13. The pull-up voltage

(VPGD) can be as high as 80V with transient capability to 100V and can be higher or lower than the

voltages at VIN and OUT.

15 Shutdown

With the circuit in normal operation, the LM5066 can be shutdown by grounding the UVLO/EN pin or by

clicking the ON/OFF button on the LM5066 block representation in the GUI.

16 Board Layout and Probing Cautions

Refer to the product datasheet for detailed layout guidelines. For most applications the layout of this

evaluation module as detailed in the PC Board Layout section of this document should be sufficient to

provide a working solution with accurate telemetry. The following should be kept in mind when the board is

powered:

1. Use CAUTION when probing the circuit to prevent injury as well as possible damage to the circuit.

2. At maximum load current (16.7A), the wire size and length used to connect the power source and the

load become very important. The wires connecting this evaluation board to the power source should be

a heavy gauge and twisted together to minimize inductance in those leads. The same applies for the

wires connecting this board to the load. This recommendation is made in order to minimize high

voltage transients from occurring when the load current is shut off.

3. A 60V TVS diode located as close as possible to the LM5066 VIN and GND pins provides the critical

function of clamping inevitable input voltage overshoot when Q

turns off at high currents. If operation

above 60V is required, the TVS will need to be replaced with a TVS rated at a higher standoff voltage.

Always verify the TVS by performing a worst-case current limit at the maximum input voltage and

monitoring the resulting input voltage surge. The TVS should be able to clamp the input below 100V in

all cases.

4. The ground points for the UVLO/EN, OVLO and FB resistor networks are tied directly to a via where

the LM5066 is conneced to the ground plane. The ground for the temperature sensing transistor, Q2, is

also tied back to the LM5066 ground.

5. Input capacitor, C1, local to the LM5066 is not populated due to the input current spike to charge this

AN-2160 LM5066 Evaluation Board SNVA487A–August 2011–Revised April 2013

Submit Documentation Feedback