Datasheet

VIN
UVLO/EN
OVLO
GND
R1
R3
R4
2.48V
2.46V
TIMER AND
GATE
LOGIC CONTROL
LM5066
R2
21 PA
20 PA
V
IN
1.1V
1 2 3 7 8
4.2 mA pulldown
Fault
Detection
GATE
Pin
Load
Current
T
I
LIMI
t
RESTART
Fault Timeout
Period
20 PA
Gate Charge
2.5
PA
3.9V
75 PA
0.3V
TIMER
Pin
www.ti.com Fault Detection & Restart
12 Fault Detection & Restart
If the load current increases to the fault level (the current limit threshold of 8.67A), an internal current
source charges the timing capacitor at the TIMER pin. When the voltage at the TIMER pin reaches 3.9V,
the fault time-out period is complete and the LM5066 shuts off Q
1
. The restart sequence then begins,
consisting of seven cycles at the TIMER pin between 3.9V and 1.1V, as shown in Figure 11. When the
voltage at the TIMER pin reaches 0.3V during the eighth high-to-low ramp, Q
1
is turned on. If the fault is
still present, the fault time-out period and the restart sequence repeat.
Figure 11. Fault Time-out and Restart Sequence
The waveform at the TIMER pin can be monitored at the TIMER test point. On this evaluation board, the
initial fault time-out period is 8.2 ms and the restart time is 1.4 seconds.
13 UVLO and OVLO Input Voltage Threshold
Programming the UVLO threshold sets the minimum system voltage to enable Q
1
. If VIN is below the
UVLO thresholds, Q
1
is switched off, denying power to the load. Programmable hysteresis is adjustable by
changing the value of R1.
The UVLO thresholds are set with two resistors (R1, R2) as shown in Figure 12 .
The OVLO threshold sets the maximum voltage that can be present on the input before the device turns
off the series pass device. The OVLO threshold is set with the two resistors (R3, R4). The hysteresis
voltage is set by the internal 21 µA current source and the value of R3.
Figure 12. Programming the UVLO Threshold
11
SNVA487A–August 2011–Revised April 2013 AN-2160 LM5066 Evaluation Board
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