Datasheet
t1
0
0
t2
t3
a)
Power Limit
Source Voltage-toGate -
V
DS
t
ON
0
V
SYS
P
LIM
V
GATE
V
GSL
V
TH
P
MOSFET
0
I
DS
Theory of Operation
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Figure 10. Power Up Using Power Limit
If the power across Q
1
does not exceed the programmed power limit, the LM5066 will also limit the drain
current to the current limit value determined by the sense resistance and the selected current limit voltage
threshold, 26 mV or 50 mV. The current limit will be maintained constant as the output voltage continues
to increase. During the current limit period, the voltage at the TIMER pin will be rising. If the TIMER
voltage reaches 3.9V before the current limit time has expired, the device will shut down and retry
according to the programmed retry configuration. If the TIMER does not expire, the output voltage will rise
and the drain current needed to charge the output capacitance will reduce. The output voltage will
continue to rise towards the the input voltage (V
DS
decreases to near zero), and the drain current then
reduces to a value determined by the load. Q
1
’s gate-to-source voltage then increases to its final value.
The circuit is now in normal operation mode.
Monitoring of the load current for faults during normal operation is accomplished using the current limit
circuit described above. If the load current increases to 8.67 Amps (26 mV across R
S
), Q
1
’s gate is
controlled to prevent the current from increasing further. When current limiting takes effect, the fault timer
limits the duration of the fault. At the end of the fault time-out period Q
1
is shut off, denying current to the
load. The LM5066 then initiates a restart every 1.4 seconds. The restart consists of turning on Q
1
and
monitoring the load current to determine if the fault is still present. After the fault is removed, the circuit
powers up to normal operation at the next restart. If the retry setting is changed to a limited number of
retrys, it will stop retrying after the programmed number of retrys occur, and keep Q
1
shut off until
UVLO/EN is toggled, or the output is turned off, and then on via PMBus.
In a sudden overload condition (e.g. when the output is shorted to ground), it is possible the current could
increase faster than the response time of the current limit circuit. In this case, the circuit breaker sensor
shuts off Q
1
’s gate rapidly when the voltage across R
S
reaches 50 mV. When the current reduces to the
current limit threshold, the current limit circuitry then takes over.
The PGD logic level output is low during turn-on and switches high when the output voltage at OUT is
above 40V. PGD switches low when the voltage at OUT is below 37V. The high level voltage at PGD can
be any appropriate voltage up to +80V and can be higher or lower than the voltages at VIN and OUT.
The UVLO thresholds are set by resistors R1 and R2, the OVLO thresholds are set by R3 and R4, and the
PGD thresholds are set by resistors RFB1 and RFB2 (R
20
and R
7
on the board). Internal current sources
at the UVLO, OVLO, and FB pins provide hysteresis for these thresholds.
10
AN-2160 LM5066 Evaluation Board SNVA487A–August 2011–Revised April 2013
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