User's Guide SNVA481A – October 2011 – Revised May 2013 AN-2143 LM5064 Evaluation Kit 1 Introduction The LM5064EVK evaluation module provides the power design engineer with a fully functional intelligent monitoring and protection controller board designed for negative voltage systems. This application note describes the various functions of the board, how to test and evaluate it, and how to use the GUI design tool to change the components for a specific application.
Simplified Schematic 3 www.ti.com Simplified Schematic GND1 (+) GND2 (+) R1 200 kŸ R3 191 kŸ VCC UVLO/EN VAUXH OVLO PGD R2 16.9 kŸ R4 8.25 kŸ 60V 5.0SMDJ60A VAUX R5 280 kŸ R6 10.0 kŸ SDAI SDAO SCL SMBA OUT LM5064 GATE CL RETRY ADR0 ADR1 ADR2 VAUX SENSE + + 100 µF CO1 100 µF CO2 D1 B3100-13-F SENSE_ K VEE_K VEE VREF TIMER CREF 1 µF VDD PWR CVDD CT 0.15 µF 1 µF DIODE RPWR 30.1 kŸ DTEMP CMPT3904 RS 0.003 Q1 FDB047N10 VEE (-) VEE_OUT (-) Figure 1.
Simplified Schematic www.ti.com GND1_S GND2_S RIN 0Ÿ GND1 (+) R1 200 kŸ UVLO/ EN R3 191 kŸ CIN 10 nF VCC UVLO/EN VAUXH OVLO OVLO PGD SDAI SDAO SCL SMBA 60V 5.0SMDJ60A VAUX R5 280 kŸ R6 10.0 kŸ VEE PGD OPEN R4 8.25 kŸ GND2 (+) CAXH OPEN VEE U1 R2a R2 16.
Getting Started 4 www.ti.com Getting Started The LM5064 evaluation kit hardware is shown in Figure 3. The LM5064EVK is supplied with the PMBus address set to 0x16 as dictated by the switch configuration of the ADR0, ADR1, and ADR2 jumper connections. Figure 3. Connection Illustration The first step to evaluate the telemetry features of LM5064 is to install the GUI software. The software is included on a CD in the evaluation kit and is titled PMBManager-x.x.x-xxxxxxxx.
Device Evaluation www.ti.com Figure 4. Device Selector The device should be detected on the PMBusand the initial load screen should appear as shown in Figure 5. Figure 5. Initial GUI Screen If a device is not detected, an option is provided to rescan, ignore, or exit the GUI.
Device Evaluation www.ti.com Device Telemetry Telemetry Plotter Device Information Display Options Design Tool Device Configuration Figure 6. LM5064 Block Level Representation Double click on the detected device ID (NSC-LM5064-AA) to display a block level representation of the device as shown in Figure 6. The block level view of the device provides a display of all the telemetry data as well as most of the faults and warnings supported by the device.
GUI Event Log www.ti.com Figure 7. LM5064 Telemetry Display Options Note that turning off the various warning options does not mask the faults from issuing an SMBus alert - it just does not display them if they occur. The device is capable of masking various faults and this functionality can be setup in the device configuration panel. 7 GUI Event Log A GUI event log is provided to keep track of GUI configuration changes and device fault events.
Plotting Telemetry Data 8 www.ti.com Plotting Telemetry Data To enable telemetry data plots click on the sine wave icon located on the LM5064 block representation. After enabling the telemetry, a prompt will appear requesting entry of the GUI sample rate, plot rate, and plot depth. For most cases the default rates and depths will be acceptable. The plotting tool allows the user to select the desired data to be plotted. Up to two different parameters may be plotted at the same time as shown in Figure 8 .
Configuring the LM5064 Device www.ti.com Figure 9.
Customizing the Design www.ti.com The Warning and Fault Threshold tab allows configuration of the input under-voltage, input over-voltage, output under-voltage, input over-current, input power, and over temperature warnings. This tab also allows adjustment of the over-temperature fault threshold. Fault threshold for the input over- and under-voltage, current limit, power limit, and power good are set by the hardware design.
GUI Register Page www.ti.com Design inputs are keyed in on the left side following steps 1 though 5. General operating conditions should be entered in step 1 of the design tool. These inputs help set bounds on the startup time and application voltage ranges. Step 2 allows the user to tailor the MOSFET protection features to be specific to the target application. Current limit is pin-configurable and software configurable, and circuit breaker is software-configurable.
GUI Register Page www.ti.com Figure 11. LM5064 Register Page Telemetry is updated by clicking the Update Telemetry button. This action will update the fields under the Averaged heading and under the Immediate heading along with VAUX and PEAK PIN. Select which parameters to update by clicking in the box next to each parameter.
Theory of Operation www.ti.com signal was asserted. They are not reset or cleared by the CLEAR_FAULTS command but rather, they are re-armed, or readied, to be over-written with new values at the onset of the next SMBA signal assertion. Note that these telemetry fields and this register are not cumulative. That is, they can only be updated once after the CLEAR_FAULTS command is issued, and it will be at the first occurrence of the SMBA assertion following the CLEAR_FAULTS.
Fault Detection & Restart www.ti.com If the power across Q1 does not exceed the programmed power limit, the LM5064 will also limit the drain current to the current limit value determined by the sense resistance and the selected current limit voltage threshold, 26 mV or 50 mV. The current limit will be maintained constant as the output voltage continues to increase. During the current limit period, the voltage at the TIMER pin will be rising. If the TIMER voltage reaches 3.
UVLO and OVLO Input Voltage Threshold www.ti.com The waveform at the TIMER pin can be monitored at the TIMER test point. On this evaluation board, the initial fault time-out period is 8 ms and the restart time is 1.4 seconds. 14 UVLO and OVLO Input Voltage Threshold Programming the UVLO threshold sets the minimum system voltage to enable Q1. If VCC-VEE is below the UVLO thresholds, Q1 is switched off, denying power to the load. Programmable hysteresis is adjustable by changing the value of R1.
Performance Characteristics www.ti.com LM5064 is conneced to the VEE plane. 5. All testpoint signals are referenced to the VEE voltage. 17 Performance Characteristics VTIMER (2V/Div) VTIMER (2V/Div) VOUT (20V/Div) VOUT (20V/Div) VSYS (20V/Div) VSYS (5V/Div) IIN (5A/Div) IIN (5A/Div) Figure 15. Insertion Time Delay (40 ms/div) Figure 16. Turn-On Sequence into a 40Ω Load (40 ms/div) VTIMER (2V/Div) VGATE (5V/Div) VTIMER (2V/Div) VOUT (20V/Div) CL = 8.7A CB = 1.
Performance Characteristics www.ti.com 1.6 1.0 1.2 0.8 PIN ERROR (%) IIN ERROR (%) 0.4 0.0 -0.4 -0.8 CL=VEE 0.4 0.2 0.0 -0.2 -0.4 -0.6 -1.2 -0.8 -1.6 -50 0.6 CL=VEE 0.8 -1.0 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 21. IIN Error vs Temperature -50 -25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 22.
Bill of Materials 18 www.ti.com Bill of Materials Designator Value Description Manufacturer Part Number Qty.
Bill of Materials www.ti.com Designator Value Description Manufacturer Part Number Qty. AD0, AD1, AD2, CL, DRAIN, GATE, GND1_S, GND2_S, OVLO, PGOOD, RS+, RS-, RTRY, TIMER, UVLO, VAUX, VAUXH, VDD, VEE_OUT_S, VEE_S Test Point, TH, Miniature Keystone Electronics 5015 20 ADR0, ADR1, ADR2, CLIMIT, RETRY SWITCH SLIDE SPDT SMD J-LEAD 50 V, 100 mA Copal CJS-1201TA 5 GND1, GND2, VEE, VEE_OUT Standard Banana Jack, Uninsulated Keystone Electronics 575-8 1 H1, H2, H5, H6 Standoff, Hex, 0.
PC Board Layout 19 www.ti.com PC Board Layout Figure 23. Board Top Layer Figure 24. Board Mid Layer 1 Figure 25.
PC Board Layout www.ti.com Figure 26.
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