Datasheet

V
DS
Fault Delay =
V
TIMERH
x C
TIMER
I
TIMERH
V
DS
Fault Delay =
(V
TIMERH
- V
TMRL
) x C
TIMER
I
TIMERH
V
DS
Fault Delay =
V
TIMERH
x C
TIMER
I
TIMERL
LM5060
SNVS628F –OCTOBER 2009–REVISED APRIL 2013 www.ti.com
FAULT DETECTION DELAY TIME
To allow the gate of the MOSFET adequate time to change, and to allow the MOSFET to conduct currents
beyond the protection threshold for a brief period of time, a fault delay timer function is provided. This feature is
important when drive loads which require a surge of current in excess of the normal ON current upon start up, or
at any point in time, such as lamps and motors. A single low leakage capacitor (C
TIMER
) connected from the
TIMER (pin 7), to ground sets the delay time interval for both the V
GS
status detection at start-up and for the
subsequent V
DS
Over-Current fault detection.
When the LM5060 is enabled under normal operating conditions the timer capacitor will begin charging at a 6 μA
(typical) rate while simultaneously charging the gate of the external MOSFET at a 24 μA (typical) rate. The gate-
to-source voltage (V
GS
) of the external MOSFET is expected to reach the 5V (typical) threshold before the timer
capacitor has charged to the V
TMRH
threshold (2V typical) in order to avoid being shutdown.
While V
GS
is less than the typical 5V threshold (V
GATE-TH
), the V
DS
start-up fault delay time is calculated from:
where
• I
TMRL
is typically 6 μA and V
TMRH
is typically 2V (3)
If the C
TIMER
value is 68 nF (0.068μF) the V
GS
start-up fault delay time would typically be:
V
DS
Fault Delay = ((2V x 0.068 μF) / 6 μA) = 23 ms (4)
When the LM5060 has successfully completed the start-up sequence by reaching a V
GS
of 5V within the fault
delay time set by the timer capacitor (C
TIMER
), the capacitor is quickly discharged to 300mV (typical) and the
charge current is increased to 11 μA (typical) while the gate of the external MOSFET is continued to be charge at
a 24 μA (typical) rate. The external MOSFET may not be fully enhanced at this point in time and some additional
time may be needed to allow the gate-to-source voltage (V
GS
) to charge to a higher value. The drain-to-source
voltage (V
DS
) of the external MOSFET must fall below the V
DSTH
threshold set by R
S
and I
SENSE
before the timer
capacitor has charged to the V
TMRH
threshold (2V typical) to avoid a fault.
When V
GS
is greater than the typical 5V threshold (V
GATE-TH
), the V
DS
transition fault delay time is calculated
from:
where
• I
TMRH
is typically 11 μA
• V
TMRH
is typically 2V
• V
TMRL
is typically 300 mV (5)
If the C
TIMER
value is 68 nF(0.068 μF) the V
DS
transition fault delay time would typically be:
V
DS
Fault Delay = (((2V-0.3V) x 0.068 μF) / 11 μA) = 10 ms (6)
Should a subsequent load current surge trip the V
DS
Fault Comparator, the timer capacitor discharge transistor
turns OFF and the 11 μA (typical) current source begins linearly charging the timer capacitor. If the surge current,
with the detected excessive V
DS
voltage, lasts long enough for the timer capacitor to charge to the timing
comparator threshold (V
TMRH
) of typically 2V, the LM5060 will immediately discharge the MOSFET gate and latch
the MOSFET off. The V
DS
fault delay time during an Over-Current event is calculated from:
where
• I
TMRH
is typically 11 μA
• V
TMRH
is typically 2V (7)
If the C
TIMER
value is 68 nF(0.068 μF) the V
DS
Over-Current fault delay time would typically be:
V
DS
Fault Delay = ((2V x 0.068 μF) / 11 μA) = 12 ms (8)
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