Datasheet

180 mV (hysterisis)

UVLO

up to 65V

1.6V (UVLO

)

LM5060

SNVS628F –OCTOBER 2009–REVISED APRIL 2013

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In addition to the programmable UVLO function, an internal Power-On-Reset (POR) monitors the voltage at the

VIN pin and turns the MOSFET Off when VIN falls below typically 5.10V.

Figure 26. Under-Voltage Lock-Out Threshold Levels

OVER-VOLTAGE PROTECTION (OVP)

The Over-Voltage Protection function will turn off the external N-Channel MOSFET if the OVP pin voltage is

higher than the OVP

threshold (typically 2V). A resistor divider made up with R8 and R9, shown in Figure 21,

sets the Over-Voltage Protection threshold. An internal 9.6 µs timer filters the output of the Over-Voltage

Comparator to prevent noise from triggering an OVP event. An OVP event lasting longer than typically 9.6 µs will

cause the GATE pin to be discharged with an 80 mA current sink and will cause the capacitor on the TIMER pin

to be discharged.

If the Over-Voltage Protection function is not needed, the OVP pin should be connected to GND. The OVP pin

should not be left floating.

RESTART AFTER OVP EVENT

After the OVP function has been activated and the gate of the external N-Channel MOSFET has been pulled low,

the OUT pin is likely to be low as well. However, an OVP condition will not cause the V

Fault Comparator to

latch off of the LM5060 because the capacitor on the TIMER pin is also discharged during an OVP event. After

the OVP pin falls below the lower threshold (typically 1.76V), the LM5060 will re-start as described in the normal

start-up sequence and shown in Figure 22. The EN, VIN, or UVLO pins do not need to be toggled low to high to

re-enable the MOSFET after an OVP event.

nPGD Pin

The nPGD pin is an open drain connection that indicates when a V

fault condition has occurred. If the SENSE

pin voltage is higher than the OUT pin voltage the state of the nPGD pin will be high impedance. In the typical

application, as shown in Figure 21, the voltage at the nPGD pin will be high during any V

fault condition. The

nPGD state is independent of the fault timer function. The resistance R4 should be selected large enough to

safely limit the current into the nPGD pin. Limiting the nPGD low state current below 5 mA is recommended.

Product Folder Links: LM5060