Datasheet

+
+
1 2 3 4 5
6 7 8LINE GATE
INN
INP/VSS
VCC OFF nFGD
INP/VSS
TP1
D1
60V
C3
1 PF
C1
0.1 PF
R1
10.0 k:
Q1
IRF7495
SD
G
1 2 3 4 5
6 7 8LINE GATE
INN
INP/VSS
VCC OFF nFGD
INP/VSS
TP2
D2
60V
C4
1 PF
C2
0.1 PF
R2
10.0 k:
Q2
IRF7495
SD
G
S1
D3
5.1V
D4
68V
C5
22 PF
C6
22 PF
R3
10.0 k:
J1
J2
J3
J4 J5
J6
+OUT
-OUT
IN A+
IN B+
IN A-
IN B-
U1
LM5051
U2
LM5051
LINE
VCC
nFGD
OFF
GATE
INP/VSS
INP/VSS
INN
1
2
3
4
5
6
7
8
LM5051
MA
www.ti.com Off TEST Push-Button, S1
Device Pin 5 is internally connected to Device Pin 7
Figure 6. Connection Diagram
Figure 7. Schematic Diagram
5
SNVA483B–October 2011–Revised May 2013 AN-2148 LM5051MAEVAL Evaluation Board
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