Datasheet

-20 -10 0 10 20 30 40 50 60 70 80
-2
0
2
4
6
8
10
12
14
VOLTS (V)
TIME (s)
V
OFF
=1.50V
INN
OFF
GATE
nFGD
-100 0 100 200 300 400 500 600 700
-2
0
2
4
6
8
10
12
14
VOLTS (V)
TIME (ns)
V
OFF
= 1.50V
INN
OFF
GATE
nFGD
Off TEST Push-Button, S1 www.ti.com
Figure 4. OFF pin Going High, Gate OFF
Typical behavior when the TEST button is released is shown in Figure 5. In this case, the OFF pin relies
on the internal pull-down (typically 4.6 µA) to discharge any stray capacitance, as well as the probe
capacitance. Once the OFF pin has fallen below the V
OFF(IL)
threshold, the gate drive circuitry will become
active. Since, in this case, the INN pin is well below the V
SD(REV)
threshold the MOSFET gate will
immediately begin charging. As the gate voltage increases the INN pin voltage will fall below the V
SD(TST)
threshold and the nFGD pin will go high. Note that the gate voltage may not rise all the way to the
maximum voltage, since the V
SD(REG)
threshold needs to be exceeded for that to happen, see Figure 3. The
gate voltage may initially settle at some intermediate value and then slowly rise as internal heating of the
MOSFET causes the R
DS(ON)
to rise which, in turn, causes the drain to source voltage to rise and, in
response, the LM5051 increases the gate voltage in an effort to keep the drain to source voltage regulated
at the V
SD(REG)
threshold.
Figure 5. OFF pin Going Low, Gate Drive Active
4
AN-2148 LM5051MAEVAL Evaluation Board SNVA483B–October 2011–Revised May 2013
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