Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsDev KitsPCB design board

0 1 2 3 4 5

100

120

140

160

(mV)

(A)

GATE

(V)

GATE

SD(REG)

Q1 = IRF7495PDF

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Off TEST Push-Button, S1

With Q2 off, the output voltage will fall until it is just below the second supply voltage by the V

SD(REV)

threshold voltage. When this happens, the gate of the MOSFET (Q1) will begin charging from the LM5051

(U1). Note that the Q1 gate voltage may not rise all the way to the maximum voltage, since the V

SD(REG)

threshold will needs to be exceeded for that to happens, see Figure 3. The gate voltage may initially settle

at some intermediate value and then slowly rise as internal heating of the MOSFET causes the R

DS(ON)

rise which, in turn, causes the drain to source voltage to rise and, in response, the LM5051 increases the

gate voltage in an effort to keep the drain to source voltage regulated.

Figure 3. Gate Drive vs Drain to Source Voltage

6 Off TEST Push-Button, S1

The single push-button (S1) provided on the LM5051 evaluation board is used to control the operation of

both LM5051 devices. The LM5051 Eval board has an on-board 5V (with respect to the 48V- OUT

terminal) reference that is used to drive the OFF pins of both LM5051 devices to shut down the gate

drives, as well as provide a voltage bias for the nFGD status output pins. For more details, see the

LM5051 Low Side OR-ing FET Controller Data Sheet (SNVS702).

In normal operation, the LM5051 OFF pin is left open. The LM5051 internal OFF pin pull-down will ensure

that both of the LM5051 devices are operating in the default active mode.

To disable both LM5051 devices, simply press the TEST push-button. Typical behavior is shown in

Figure 4 and Figure 5.

The typical OFF behavior is shown in Figure 4. Pressing the TEST button applies approximately 5V to the

OFF pin of both LM5051 devices. After the OFF pin rises above the V

OFF(IH)

threshold the MOSFET gate

will be quickly discharged. As the gate discharges, the voltage across the MOSFET drain to source pins

will increase. Since all measurements are referenced to the LM5051 INP/VSS pin, the INN pin will appear

to be going negative. When the INN pin has gone more negative than the V

SD(TST)

threshold (typically -

260mV), the nFGD pin go low. The INN pin voltage will be clamped at about -600mV by the MOSFET

body diode.

SNVA483B–October 2011–Revised May 2013 AN-2148 LM5051MAEVAL Evaluation Board

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