Datasheet

LM5046
www.ti.com SNVS703G –FEBRUARY 2011–REVISED MARCH 2013
Electrical Characteristics
Limits in standard typeface are for T
J
= 25°C only; limits in boldface type apply the junction temperature range of -40°C to
+125°C. Unless otherwise specified, the following conditions apply: VIN = 48V, RT = 25kΩ, RD1=RD2=20kΩ. No load on
HO1, HO2, LO1, LO2, SR1, SR2, COMP=0V, UVLO=2.5V, OVP=0V, SSOFF=0V.
Symbol Parameter Conditions Min Typ Max Units
Startup Regulator (VCC pin)
V
CC1
VCC voltage I
CC
= 10mA (SSSR<1V) 9.3 9.6 9.9 V
V
CC2
VCC voltage I
CC
= 10mA (SSSR>1V) 7.5 7.8 8.1 V
I
CC(Lim)
VCC current limit V
CC
= 6V 60 80 mA
I
CC(ext)
VCC supply current Supply current into VCC from an externally 4.6 mA
applied source. V
CC
= 10V
VCC load regulation I
CC
from 0 to 50 mA 35 mV
V
CC(UV)
VCC under-voltage threshold Positive going VCC V
CC1
–0.2 V
CC1
–0.1 V
VCC under-voltage threshold Negative going VCC 5.9 6.3 6.7 V
I
IN
VIN operating current 4 mA
VIN shutdown current V
IN
=20V, V
UVLO
=0V 300 520 µA
V
VIN
=100V, V
UVLO
=0V 350 550 µA
VIN start-up regulator leakage V
CC
=10V 160 µA
Voltage Reference Regulator (REF pin)
V
REF
REF Voltage I
REF
= 0mA 4.85 5 5.15 V
REF voltage regulation I
REF
= 0 to 10mA 25 50 mV
I
REF(Lim)
REF current limit V
REF
= 4.5V 15 20 mA
V
REFUV
V
REF
under-voltage threshold Positive going V
REF
4.3 4.5 4.7 V
Hysteresis 0.25 V
Under-Voltage Lock Out and shutdown (UVLO pin)
V
UVLO
Under-voltage threshold 1.18 1.25 1.32 V
I
UVLO
Hysteresis current UVLO pin sinking current when 16 20 24 µA
V
UVLO
<1.25V
Under-voltage standby enable UVLO voltage rising 0.32 0.4 0.48 V
threshold
Hysteresis 0.05 V
V
OVP
OVP shutdown threshold OVP rising 1.18 1.25 1.32 V
OVP hysteresis current OVP sources current when OVP>1.25V 16 20 24 µA
Soft-Start (SS Pin)
I
SS
SS charge current V
SS
= 0V 16 20 24 µA
SS threshold for SSSR charge I
COMP
<800µA 1.93 2.0 2.20 V
current enable
SS output low voltage Sinking 100µA 40 mV
SS threshold to disable switching 200 mV
I
SSSR
SSSR charge current V
SS
>2V, I
COMP
<800µA 16 20 24 µA
I
SSSR-DIS1
SSSR discharge current 1 V
UVLO
<1.25V 54 65 75 µA
I
SSSR-DIS2
SSSR discharge current 2 V
RES
>1V 109 125 147 µA
SSSR output low voltage Sinking 100µA 50 mV
SSSR threshold to enable SR1/SR2 1.2 V
Current Sense Input (CS Pin)
V
CS
Current limit threshold 0.710 0.750 0.785 V
CS delay to output 65 ns
CS leading edge blanking 50 ns
R
CS
CS sink impedance (clocked) Internal FET sink impedance 18 45 Ω
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