Datasheet

LM5046
www.ti.com SNVS703G –FEBRUARY 2011–REVISED MARCH 2013
PIN DESCRIPTIONS (continued)
TSSOP WQFN
Name Description Application Information
Pin Pin
7 3 REF Output of a 5V reference Maximum output current is 15mA. Locally decouple with a 0.1µF
capacitor.
8 4 RT/SYNC Oscillator Frequency Control and The resistance connected between RT and AGND sets the
Frequency Synchronization oscillator frequency. Synchronization is achieved by AC coupling a
pulse to the RT/SYNC pin that raises the voltage at least 1.5V
above the 2V nominal bias level.
9 5 AGND Analog Ground Connect directly to the Power Ground.
10 6 RD1 Passive to Active Delay The resistance connected between RD1 and AGND sets the delay
from the falling edge of HO1/SR1 or LO1/SR2 and the rising edge
of LO1 or HO1 respectively.
11 7 RD2 Active to Passive Delay The resistance connected between RD2 and AGND sets the delay
from the falling edge of LO2 or HO2 and the rising edge of HO2 or
LO2 respectively.
12 8 RES Restart Timer Whenever the CS pin exceeds the 750mV cycle-by-cycle current
limit threshold, 30µA current is sourced into the RES capacitor for
the remainder of the PWM cycle. If the RES capacitor voltage
reaches 1.0V, the SS capacitor is discharged to disable the HO1,
HO2, LO1, LO2 and SR1, SR2 outputs. The SS pin is held low until
the voltage on the RES capacitor has been ramped between 2V and
4V eight times by 10µA charge and 5µA discharge currents. After
the delay sequence, the SS capacitor is released to initiate a normal
start-up sequence.
13 9 SS Soft-Start Input An internal 20µA current source charges the SS pin during start-up.
The input to the PWM comparator gradually rises as the SS
capacitor charges to steadily increase the PWM duty cycle. Pulling
the SS pin to a voltage below 200mV stops PWM pulses at HO1,2
and LO1,2 and turns off the synchronous rectifier FETs to a low
state.
14 10 SSSR Secondary Side Soft-Start An external capacitor and an internal 20µA current source set the
soft-start ramp for the synchronous rectifiers. The SSSR capacitor
charge-up is enabled after the first output pulse and SS>2V and
Icomp <800µA
15 11 SSOFF Soft-Stop Disable When SS OFF pin is connected to the AGND, the LM5046 soft-
stops in the event of a VIN UVLO and Hiccup mode current limit
condition. If the SSOFF pin is connected to REF pin, the controller
hard-stops on any fault condition. Refer to Table 2 for more details.
19 15 SR2 Synchronous Rectifier Driver Control output for synchronous rectifier gate. Capable of peak
sourcing 100mA and sinking 400mA.
21 17 VCC Output of Start-Up Regulator The output voltage of the start-up regulator is initially regulated to
9.5V. Once the secondary side soft-start (SSSR pin) reaches 1V,
the VCC output is reduced to 7.7V. If an auxiliary winding raises the
voltage on this pin above the regulation set-point, the internal start-
up regulator will shutdown, thus reducing the IC power dissipation.
22 18 PGND Power Ground Connect directly to Analog Ground
23, 20 19, 16 LO1, LO2 Low Side Output Driver Alternating output of the PWM gate driver. Capable of 1.5A peak
source and 2A peak sink current.
24 20 SR1 Synchronous Rectifier Driver Control output for synchronous rectifier gate. Capable of peak
sourcing 100mA and sinking 400mA.
25, 18 21, 14 BST1,2 Gate Drive Bootstrap Bootstrap capacitors connected between BST1,2 and SW1,2
provide bias supply for the high side HO1,2 gate drivers. External
diodes are required between VCC and BST1,2 to charge the
bootstrap capacitors when SW1,2 are low.
26, 17 22, 13 HO1,2 High Side Output Driver High side PWM outputs capable of driving the upper MOSFET of
the bridge with 1.5A peak source and 2A peak sink current.
27, 16 23, 12 HS1,2 Switch Node Common connection of the high side FET source, low side FET
drain and transformer primary winding.
28 24 VIN Input Power Source Input to the Start-up Regulator. Operating input range is 14V to
100V. For power sources outside of this range, the LM5046 can be
biased directly at VCC by an external regulator.
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